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DDR3 length matching

Zeb
Intellectual 380 points

I would need some information regarding our design's DDR3 routing. I have read the DDR3 design papers, especially the SPRABI1B. Regarding the relation of address, control and clock is not very clearly explained in this manual so I would like you to review what we have.

Below are the routing lengths, please have a look.


DDR3 layout configuration, 2GB bytes of memory in 72bit configuration (including ECC). Fly-by topology, memory speed 1600MHz. Processor is K2L.

Data lane lengths:

Data lane 0: 1398 mils
Data lane 1: 1630 mils
Data lane 2: 1264 mils
Data lane 3: 1047 mils
Data lane 4: 1650 mils
Data lane 5: 972 mils
Data lane 6: 1047 mils
Data lane 7: 1453 mils
Data lane ECC: 1106 mils

Within each data lane, all lines are matched witin +-2 mils (with DQSN & DQSP diff line routes within +-1 mils)

Address & control lengths (fly-by):

From SOC to 1st DDR3 memory chip: 2165 mils

Clock (fly-by):

From SOC to 1st DDR3 memory chip: 2287 mils


Routing distance in between eacg DDR chip is 492 mils (applies for address, control and clock). Terminations from last DDR3 chip are all less than 500 mils.

Both address & control group signals are length matched. Same applies to clock, differential pair has equal lenght in both routes. What worries the most is the length mismatch in between clock and address & control....

  • 0
    TI__Guru**** 161600 points
    Hi,

    This has been forwarded to the hw experts. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    Zeb,

    The fly-by length matching requirements in SPRABI1B must be met.  You can reference JEDEC documentation if more information is needed to understand fly-by routing.  The attached report shows an application report showing that the rules have been met.  Please generate a report such as this to show that the rules have been met.  Your CAD tool may actually be able to generate this for you.

    Tom

    6886.EVM_DDR3_Rules.xls

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 37500 points

    Hello,

       The  DDR3 Design Requirements for Keystone Devices

            4.3.1.4,5,6,7

                  Address and command signals are routed in a group, length matched to within 10mils,  Stubs < 80mil

                 

                  Clock to Address and Control group within 20mil of the group clock.  DiffClk matching to 1mm, clock pair stub < 40mil

     

                  DataLine, DQS routing within a group are within 10mil, DQS data differential to within 1mil

                  Table 14 matches the bytelane data to the DQS strobe

     

           4.3.1.9 this discusses how we determine if the DDR clock is inverted.   It establishes the max delay as 4 DDR3 clock periods. 

       Keystone 2 hardware design guide – refers to the DDR guide

    a)      Each Data Lane Group has matching with within 2mil, which is FINE, specification is 10mil.

    b)      Address, Control, are matched to group within 10mil, and Address,Control to  clock within 20mil , this is violated for K2L to first DDR3

    c)      Address, Control, are matched to within 10mil for group, and group to clock within 20mil for other DDR3 to termination – this is OK

     

    Comparing the TCI6630K2L EVM DDR3 layout to the customer layout can also provide an additional reference.  The layout for the EVM is available

    on the einfochips website.  

    Regards,

    Joe Quintal