C5505 UART 16x Sampling Points

Hi,

As per the spec, Each bit lasts 16 bclk cycles and is sampled in the 8th cycle. 

Regards

 Vasanth

Vasanth,

Unfortunately this does not answer my question. We know based on a previous conversation with the C5000 product group that the UART takes three samples and averages the three to get the final bit value. I understand that at least 1 of these samples happens on the 8th cycle, but what cycle are the other two samples on?

Thanks,
Stuart

Stuart,

Spec doesn't provide more information than the above. This need to be further looked into design database. I will check on this and get back.

Regards

 Vasanth

 

Stuart,

As per my understanding of the design, below is how the sample and vote works,

 

The vote is considered at the eighth clock edge of bit clock. So the previous 3 consecutive samples are actually considered for deciding on whether the bit is either 1 or 0, (though as per design the sample happens continuously at every edge of the bit clock, but prior to 8^th edge is where actual samples are considered) .

Hope this clarifies.

Regards

 Vasanth

 

Vasanth,

Thank you for this information.  It has led to another question.

How is the start bit recognized with respect to the sample clock?

We are looking for this information in order to determine if across 10 bits (1 Start, 8 data, 1 stop) we are able to meet timing in a system where a 2.000 Mbaud UART is interfaced with the C5505 whose UART is running at 2.048 Mbaud.  There are also optocouplers between the UARTs withc add a little distortion to the waveform, which we will also account for in the assessment.

Thanks,

Stuart

Stuart,

 

 

The start bit is detected by the vote bit been sampled for zero for start condition.

 

The vote is checked for low from its initial high state, this is considered at the eighth clock edge of bit clock (7^th if its counted from 0). So the previous 3 consecutive samples are actually considered for deciding on whether the bit is either 1 or 0.If the vote is found zero then this is the start bit.  It would then elapse eight more cycles of bit clock before proceeding to receive data state (to receive the other data bits).

 

Hope this information helps.

 

Regards

 Vasanth

Hi Vasanth, could you confirm a few things based on your previous response?

• Is the voting mechanism a simple majority vote, i.e. 2 or more logic level low = low, and 2 or more logic level high = high?
• Is the beginning of the start bit considered to be the first sample clock that the received data is logic level low?
• I have tried to capture your description in your previous post in a drawing, could you check to see that I have interpreted your answer correctly? I want to make sure I have specified the correct number of sample clocks between events. I am surprised that bit 7 is the determining bit since it is not in the center, perhaps I have drawn it wrong?

the dotted line represents when the first logic low is sampled, the red lines are the voting sample points, and the green line the point at which the bit value is determined.

Hi,

Here is my answers for your Questions.

• Is the voting mechanism a simple majority vote, i.e. 2 or more logic level low = low, and 2 or more logic level high = high?

           - Yes its a mechanism of simple majority voting.

• Is the beginning of the start bit considered to be the first sample clock that the received data is logic level low?

           - Yes

• I have tried to capture your description in your previous post in a drawing, could you check to see that I have interpreted your answer correctly? I want to make sure I have specified the correct number of sample clocks between events. I am surprised that bit 7 is the determining bit since it is not in the center, perhaps I have drawn it wrong?

            - Yes,  as mentioned earlier the voting is decided on the eighth clock edge which is in the center. The your drawing looks correct with respect to previous consecutive samples being considered.

Hope this clarifies.

Regards

 Vasanth.