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MMU issue

Nhan Nguyen55
Intellectual 300 points
Other Parts Discussed in Thread: OMAPL138, SYSBIOS

Dear all,

My project is using OmapL138 and SYSBIOS on aRM. I have one problem with MMU module. It set enable by default on SYS/BIOS:

// Enable the MMU (Required for L1 data caching)
Mmu.enableMMU = true;

My scenario is I want to modify a value in physical address is 0x8000000. but when MMU module is enabled, the value is not change. (I view it on memory brower window, run debug mode). I have to disable MMU, it wil change. 

How to modify the value when MMU module is still enable? Any help? 

Thanks,

Nhan

  • 0
    TI__Guru* 96960 points
    Can you attach your configuration of the MMU? Also, what version of SYS/BIOS are you using?

    Todd
  • 0
    Guru 92251 points

    Nhan Nguyen55 said:
    My scenario is I want to modify a value in physical address is 0x8000000. but when MMU module is enabled, the value is not change. (I view it on memory brower window, run debug mode).

    Do you need to force a value to be modified in physical memory to be accessed by a different master than the ARM9 core?

    If so, possible options are:

    a) Configure the MMU so that the the MMU page at address 0x8000000 is marked as not cacheable.

    b) Leave the MMU page at address 0x8000000 as cacheable, and after modifying the address in the ARM9 core call the Cache_wb() or Cache_wbInv() functions in the ti.sysbios.family.arm.arm9.Cache module to cause the address to be written from the ARM9 cache to physical memory.

  • 0 in reply to Chester Gillon
    Intellectual 300 points
    Hi Chester Gillon,

    Thanks for your support.
    I fix my issue by force the address 0x80000000 as non cachable:

    var peripheralAttrs = { type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
    bufferable : false, // bufferable
    cacheable : false, // cacheable
    }; // Define the base address of the 1 Meg page the peripheral resides in.

    var peripheralBaseAddr = 0x80000000;
    Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

    Regards,
    Nhan.