• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 1029 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DM365 EVM EMIF

Nara Won
Intellectual 1605 points

Hi Experts,

Customer is trying to connect a device through DM365 EMIF on DM365 EVM.

They have following questions.

1)  I cannot see in the EVM litterature how we would "connect" the signals from J23 to the processor pins. For example pin 6 of J23 is CPLD.CONN_GI06 and I cannot find which CPLD registers we need to configure that pin. Could you please clarify?

 

2) On the EMIF interface, I think I understand how it works but I am not sure which address space is available on the external connector (J14) and whether further address decoding is required or not. EM_CE0 and EM_CE1 are available on the connector but EM_CE0 is assigned to the Flash and EM_CE1 is used for the CPLD... Can you suggest which address space we should be using on the EMIF bus and how to decode it?

 

  • 0
    TI__Genius 9490 points

    Nara,

    Here are the answers/suggestions:

    1)  We will check with EVM manufacturer to see if a mapping table exists.

    2) The EVM Tech Ref guide chapter 2.1 shows the AEMIF IF breakdown and outlines the NAND/OneNAND space availabe and its mapping to CE0 space, the CPLD IF is mapped to CE1. The EVM tech reference guide figure 1-4 explains how the EM_CEx address space is mapped http://support.spectrumdigital.com/boards/evmdm365/reve/files/EVMDM365_TechRef_reve.pdf

    -The CPLD register interface and registers mapping are also detailed in section 2.1.1.2.(too much to put here) in case they need to access them.

    -Spectrum digital NAND/oneNAND tests can be used as an example to generate an AEMIF test(but they should change mode(non-NAND) and maybe re-mapp to an CEx space that is not being used)  ...\evmdm365_v1\tests\nandflash-lower

    regards,

    miguel

  • 0 in reply to Miguel A. Alanis
    TI__Genius 9490 points

    Here is the answer to question #1 and additional details on question #2.

     

    1)      The signals on J23 are just GPIO implemented in the CPLD.  They do not correlate with CPU pins.  You can set them using CPLD registers 720 and on (which are listed in the Technical Reference) but to get the right mapping of which bits in those registers go to which pins on J23 you should just browse the .vhd and .pin files in the CPLD source code on the support page.  These functions have no purpose, they are connected more or less as placeholders in case something had to be added to the CPLD later on.

    2)      The EM_CE0 and EM_CE1 signals going to J14 are the actual signals straight from the DM365.  They also go into the CPLD, where they are combined with some address decode logic to drive the NAND and OneNAND chip selects.  If you want to connect something to J14, just take the NAND chip out of its socket so it doesn’t respond to the EMIF signals at the same time as what you’re connecting.

     

    regards,

    miguel

  • 0 in reply to Miguel A. Alanis
    TI__Prodigy 240 points

    Some questions about EMIF and GPIO on DM365.

    Q1. What is EMIF_SEL pin for?

           I can’t find more information from technical data sheets.

     

    Q2.  We also want to use GPIO pin connected CPLD on J23 to trigger EDMA.

    -       Which GPIO and pin could be used for a general  purpose? We only need one pin.

        As I understand,   It looks like  CPLD connect J23 pins to DM365 like <J23Pin> ---> <CPLD> --- GPIO ---- > <DM365> as shown below.

     

                                        when "11111000"  => cpld_reg_data  <= cpld_reg_gpio0;

                                        when "11111001"  => cpld_reg_data  <= cpld_reg_gpio0;

                                        when "11111010"  => cpld_reg_data  <= cpld_reg_gpio1;

                                        when "11111011"  => cpld_reg_data  <= cpld_reg_gpio1;

                                        when "11111100"  => cpld_reg_data  <= cpld_reg_gpio2; 

                                        when "11111101"  => cpld_reg_data  <= cpld_reg_gpio2;