Short versions of my questions:
a) What is the maximum size of DDR3L memory that may be used on EMIF1 if ECC is wanted?
b) Does the ECC SDRAM require the same depth / organization as the DDR3L memories?
Long version of my questions:
1) Looking at the TRM §15.3.1 (SPRUHZ6E) Figure 15-45 and Table 15-97 I'm confused by the table's notation. for the case of EMIF "wide" mode (I assume 32-bit wide bus) is it saying I can use two 2Gbit DDR3 memories maximum? That would be 512MBytes total memory size. The notation "2x2Gb x 16-bit" confuses me - does it mean two 2Gbit memories with a x16 organization or does it mean use two 2Gbx16 = 8GByte total? The later seems incorrect since the limit is 4GByte of memory per EMIF. That said, and assuming the former (512MByte DDR3 memory) the size of the ECC memory (1Gb x 8) doesn't seem correct. Can you explain this clearly please?
2) Taking this a bit further, I looked at the AM272x GP and IDK EVMs. The GP EVM uses 4 and the IDK uses 5 of the MT41K256M16 (4Gbit: 32M x 8 banks x 16 bits). Hence the GP EVM doesn't use ECC but uses both EMIFs with 1GByte each (out of a possible 2GByte each); the IDK has 1GByte on EMIF2 and 1GByte on EMIF1 + ECC (512MB). It seems the IDK ECC is larger than it needs to be. Is this correct or am I misunderstanding something?
3) I want to maximize the available SDRAM memory on the AM5726. The AM572x datasheet (SPRS953A) §7.9 states I can use single-die DDR3 up to 8Gbit each. I was thinking of using the Micron MT41K512M16 (8Gbit: 64M x 8 bands x 16bits). If I use two on each EMIF then that gives me 2GByte per EMIF. This leads to these questions:
a) Will this much memory on EMIF1 (2GB) function with ECC if I add an appropriate sized ECC memory?
b) What size should the ECC memory be? Do I use a the same as the others MT41K512M16 (8Gbit: 64M x 8 bands x 16bits) and ignore 8 bits or do I use a MT41K1G8 (8Gbits: 128M x 8 banks x 8 bits)? Or am I off-base completely?
