Jacinto6 : Question Regarding MMC1 AC timings

Hi Mitsui-san,

I have forwarded your question to an expert.

BR,
Dobrin

Shiou Mei,

 

No, MMCHS_HCTL[2].HSPE is as below. it does NOT control default/high speed mode selection. it controls which edge is used to outputs CMD line and DAT lines.

 

In fact, From DM, high speed mode is used falling edge to output CMD/DAT line same as default mode.

 

So, both default mode and High Speed mode are used same MMCHS_HCTL[2].HSPE setting.

 

In addition, the note said

 

NOTE: Do not set this bit to 0x1 as timings cannot be met at high speeds. It is recommended to not modify it and keep its default value of 0x0.

 

So, this bit is NOT contolled default mode/High speed mode.

 

I could not find any other bit which select default mode/High speed mode.

 

BTW, I would like to confirm that the word "high speeds" in the NOTE in the HSPE bit description is pointed "high speed mode" or "higher speed mode like SDR50,SDR108 ? or both ?

 

Best Regards,

Yasuhiro Mitsui

Mitsui-san,

The settings I provided were to enable the HW for different speed mode configurations. HSPE is in general used for SDR modes, but should also be applicable to high speed as well. Let me check to see if we are limiting its use based on AC char results.

To communicate the actual frequency change, SW drivers should send CMD6 (switch command) for Function Group 1 modification. The same command can be used to update drive strength, current limit, etc. Table 4-11 "Available Functions" (snapshot attached) in the SD Simplified Spec provides details on how this is used. User should send CMD6 with Mode 1 according to Section 4.3.10 "Switch Function Command".

SD Simplified Spec can be downloaded here: members.sdcard.org/.../part1_410.pdf

Best Regards,
Shiou Mei

Shiou Mei,

 

Could you tell me the programing sequence that MMC host controllers inside the Jacinto6 switch Default mode to High Speed mode after sending CMD6 ?

 

The CMD6 is used that host requests the desired speed mode to card.

Once Card is accept it, host should be change its configuration.

Drive strength can be changed MMCHS_AC12[21:20].DS_SEL

But no speed mode configuration bit is exist.

Yes, we have UHS Mode Select at MMCHS_AC12[18:16].UHSMS. but it can not select HS mode.

 

At Section 25.5.1.2.1.7.2 MMCHS Clock Frequency Change, there is flow chart that how MMC clock such as output clock from MMC host controller is changed

But this procedure is for changing output clock.

Jacinto6 has definitely difference Setup/Hold/Delay timing for default mode and HS mode.

In my understanding, these parameter is NOT depend on Clock Frequency.

So, most probably, MMC host controllers has some mechanism which switch the mode internally.

But we don’t have any configuration bit like 0:Default Mode/1: HS mode.

How MMC host controller change it ?

 

The MMCHS_CAPA[21].HSS indicates “High speed support” capability of MMC host controller.

I’m not sure “High Speed” is higher speed mode like SDR104. Or it is exactly HS mode.

Even if it indicates HS mode, this bit is 0x1. Read 0x1: High Speed Supported.

 

Best Regards,

Yasuhiro Mitsui

Shiou Mei,

 

Could you give your comment ?

 

Summary of at this time, The programing sequence of change HS mode may

 

1)      Send CMD6 with HS mode argument.

2)      Set Drive Strength.

3)      Set some bit to change AC timing from Default mode to HS mode.

4)      Set desire MMCHS Clock.

5)      Start to access with HS mode.

 

My question is how to do step 3) above ?

There is no HS mode enable bit in the Register description of TRM.

From Data Manual, the Default mode and HS mode has different AC timing.

How do we do step 3 ?

 

Best Regards,

Yasuhiro Mitsui

Hi Mitsui-san,

I think the timing change is done automatically by the MMC/SD controller state machine when CMD6 is sent to the card but let's wait for Shiou Mei's reply.

BR,
Dobrin

Mitsui-san, Dobrin,

That's correct.  Based on the CLK frequency and the corresponding MMC configuration register settings, MMC host controller will automatically adapt to the new mode of operation.  Depending on the speed mode, on J6, customers should also take virtual timings into consideration during implementations to meet the specific speed requirements.

Can you provide more details on the current issues at hand? Does the customer see issues with timing after CLK changed to 48 MHz in 3.3V rail (High Speed mode)? 

Thanks & Regards,

Shiou Mei

Shiou Mei,

Based on the CLK frequency and the corresponding MMC configuration register settings, MMC host controller will automatically adapt to the new mode of operation.  

Yes, Basically it is usual way.
In fact, for other speed mode like SDR104, Jacinto 6 have corresponding MMC configuration register settings like MMCHS_AC12[18:16]UHSMS.
But for HS mode, such a speed mode configuration register don't exists.This is the reason why this post was submitted.

I would like to confirm that,

For HS mode, there is no register which enable HS mode.
When CMD6 mode 1 which indicate that switch to HS mode is sent to the card, the MMCHS host controller detect and identify that command. Then MMCHS controller automatically changes its AC timing.
And this mechanism is for HS mode only. Because, Jacinto 6 has UHS Mode Select bit MMCHS_AC12[18:16]UHSMS.

Right ?

Yes, this is based on our customer question. But sorry, it has some NDA items. I can not describe it on this kind of open space.

Best Regards,
Yasuhiro Mitsui

Mitsui-san,

That's correct.  MMCHS_HCTL [2] HSPE mode was initially used to change timings from Default Speed to High Speed mode, but given the internal timing limitation indicated by the note in TRM, this mode should not be used.  Hence, upon CMD6 mode 1 switching command sent to card, and the internal clock frequency changed to 48 MHz, the MMCHS host controller will be compatible to operate in the desired High Speed clock frequency.

Thanks & Regards,

Shiou Mei