The EMIF16 take too much time before write and read

I found this information in one of our e2e post:

The minimum time for entire read cycle i.e. setup + strobe + hold is 50ns.

At 1.25GHz, EMIF16 clock = CPU/6 =>  4.8ns.

So r_setup + r_strobe + r_hold = 50/4.8 = 11 rounded up.

So it takes a minimum of 11 complete CPU/6 clock cycles for one read access, so the actual time for the entire read cycle = 4.8 * 11 = 52.8ns.

For 16-bit wide interface, the theoretical max read throughput = 16/52.8 = 303.03 Mbps

At 1GHz, EMIF16 clock period = 6ns.

Using the same calculation as above, we get theoretical max read throughput = 16/54 = 296.29 Mbps

The minimum time for entire write cycle is 45ns.

Using the same procedure as for reads,

Write throughput at 1.25GHz = 16/48 (10 CPU/6 clocks) = 333.33 Mbps

Write throughput at 1GHz = 16/48 (8 CPU/6 clocks) = 333.33 Mbps

The above theoretical max throughputs will be half for an 8-bit interface.

In practice the path through the SOC to/from the EMIF16 module introduces some delays of its own, so observed throughput for reads and writes will be lower.

To give you an example of silicon testing - At CPU = 900MHz, the EMIF16 setup/strobe/hold parameters were configured to give following:

Theoretical read throughput = 240 Mbps

Theoretical write throughput = 300 Mbps

The observed throughput was closer to 236Mbps for reads and 274Mbps for writes.

• I should add that the 45ns and 50ns numbers are based on the latency of available NOR flash components in the market since NOR flash is the fastest memory. It is not a limitation of the DSP. Accordingly, please ignore my last statement about "We will clarify the minimum read/write timing parameters in the documentation". We will address your concern over extended wait. A new rev of the EMIF16 user's guide will be released soon with a lot more clarity on how to program the EMIF16 registers.
• The max throughput supported by the EMIF16 interface is (16b/8b) * CPU/6.
• For write performance the bottleneck is the memory device. So EMIF16 will be able to send data at (16b/8b) * CPU/6 if memory device is fast enough.
• I mentioned in my earlier post that the SOC introduces some delays in the switch fabric for reads. So for reads, the bandwidth is limited by the memory device and the internal delays in read return path.
• The max bandwidth at the EMIF16 pins is (16b/8b) * CPU/18.