SPI delay after chip select

Hi Scott,

I've played with the SPI on my BBB (running kernel 4.4.12) and I can confirm your finding, that there is always a some delay between the assertion of CS & the first spi clock. I've also noted that this delay is lowered when spi clock is used. Bellow picture is when using 5MHz spi clk (the delay is about 12.4 us):

However, I think this is explained in AM335x TRM, Section 24.3.2.8 Chip-Select Timing Control:

So you may need to re-configure your CHx_CONF register appropriately, in order to minimize this delay. 

Hope this helps. 

Best Regards, 
Yordan

And I am unable to set and hold CS low over multi-word transfers, because the target device (a TI ADS7920) uses the falling edge of CS to trigger each transfer

Hi,

I have another suggestion, which I think will work for you.

In am335x-boneblack.dts, I added the following node: 
  

spi1_pins: spi1_pins {
   pinctrl-single,pins = <
       0x19C (PIN_INPUT_PULLUP | MUX_MODE3) /*MCASP0_AHCLKR -> spi1_CS0*/
       0x194 (PIN_INPUT_PULLUP | MUX_MODE3) /*MCASP0_FSX -> spi1_D0*/
       0x198 (PIN_INPUT | MUX_MODE3) /*MCASP0_AXR0 -> spi1_D1*/
       0x190 (PIN_INPUT_PULLUP | MUX_MODE3) /*MCASP0_ACLKX -> spi1_SCLK*/
   >;
};

&spi1 {
   #address-cells = <1>;
   #size-cells = <0>;
   status = "okay";
   pinctrl-names = "default";
   pinctrl-0 = <&spi1_pins>;
   spidev@0 {
         #address-cells = <1>;
         #size-cells = <0>;
         spi-max-frequency = <5000000>;
         reg = <0>;
         compatible = "rohm,dh2228fv";
    };
};

Then in spi-omap2-mcspi.c I added the following settings: 
    

static void omap2_mcspi_set_master_mode(struct spi_master *master)
{
      struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
      struct omap2_mcspi_regs *ctx = &mcspi->ctx;
      u32 l;

/*
* Setup when switching from (reset default) slave mode
* to single-channel master mode
*/
    l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
    l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
    l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
+  l &= (0 << 4);
+  l &= (0 << 5);
+  l &= (0 << 6);
    mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);

    ctx->modulctrl = l;
}

The above lines: 
 l &= (0 << 4);
 l &= (0 << 5);
 l &= (0 << 6);

Set MCSPI_MODULCTRL[6:4]INITDLY = 0x0 => 0h = No delay for first SPI transfer 

As a result, upon executing: 
  root@am335x-evm:~# echo BABACECA > /dev/spidev1.0 

I got the following result: 
  

A you can see the CS asserts almost at the same time as SPI_CLK (there are only 120ns delay, which may be lowered if you increase the SPI_CLK frequency). 

Best Regards, 
Yordan