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DMA Settings of McBSP for TMS320C5517

Massa1
Expert 1065 points

Hi, all;

I am reading a program "csl_mcbsp_dma_example.c in c55_csl_3.06\ccs_v6.x_examples\mcbsp".

And I find following settings as direct-address coding.

  CSL_DMA3_REGS->DMACH0DSAL = 0x6010;

  CSL_DMA3_REGS->DMACH1SSAL = 0x6000;

In C5517 Technical Reference Manual, I can find the Memory Map, and I know McBSP Start Word Address 4000h(in CPU Space) is mapped as DMA Start Byte Address 6000h.

Then I can understand DMACH1SSAL = 0x6000 as DRRL.

However DXRL CPU Word Address is 4004h, and 4004h means (base address + 4 word).

I think DXRL may be mapped as (base address + 8 byte) and this means 0x6008.

Please teach me why 4004h is mapped to 0x6010.

Or another mean about this mapping?

Regards,

Massa

  • 0
    TI__Mastermind 30365 points
    Massa1,

    Your analysis is correct. The values in the example do seem strange.

    Does the example run as expected?
    or are you seeing weird behavior due to the current config register mapping?

    Lali
  • 0 in reply to Lalindra Jayatilleke
    Expert 1065 points
    Hi, Lali,
    Thanks for your response.

    As results of our experiment, the address 0x6010 works good as DXRL.
    But the address 0x6008 seems to work malfunctioned.

    We need right answer from TI.

    Regards,
    Massa
  • 0 in reply to Massa1
    TI__Mastermind 29550 points

    Hi Massa,

    I have confirmed your results and found out the reason why the McBSP DXRL DMA address is 0x6010 instead of 0x4004 (CPU address).

    The C5517 documentation does not include this table from the McBSP functional specification, but it should include it.

    We will have to modify the C5517 TRM to show these McBSP register addresses when using the DMA. Note that when using the CPU (polling or interrupt) the address offsets are correct in the TRM.

    DXRL = 0x6010 when using the DMA.


    Thank you for raising this issue to our attention.

    Regards,
    Mark