Other Parts Discussed in Thread: OMAPL138
In our OMAPL138 application we are planning to use the EMIFA asynchronous memory interface operating with a 16 bit data bus.
The datasheet lists the memory range for the asynchronous chip selects as 32 M.
The EMIFA users guide states that the EMIFA address pin EM_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when
interfacing to a 16-bit or 8-bit asynchronous device, the EMA_BA[1] and EMA_BA[0] pins provide the least-significant bits of the halfword or byte address, respectively.
So for the OMAPL138 which has 24 address lines EMA_A[23:0] plus two bank address lines EMA_BA[1:0]
the total accessable address range would be 16M (64MB)?