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AM571x GPMC Configuration

Other Parts Discussed in Thread: SYSCONFIG

Hi-

I am trying to configure the GPMC peripheral to interface through CS0 to an external FPGA.  I have read through the documentation and all relevant e2e posts and still cannot get any response on the chip select or data lines.  Relevant register configuration from my code is below:

#define GPMC_REGISTER_BASE_ADDR 0x50000000

#define GPMC_DATA_BASE_ADDR 0x01000000

// Configure various GPMC registers

GPMCCSConfig(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, GPMC_CS_DISABLE);

GPMCDevSizeSelect(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, GPMC_DEVICESIZE_16BITS);

GPMCAddrDataMuxProtocolSelect(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, GPMC_MUXADDDATA_NOMUX);

GPMCCSTimingConfig(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, GPMC_CS_TIMING_CONFIG(20, 20, GPMC_CS_EXTRA_NODELAY, 0));

GPMCRdAccessAndCycleTimeTimingConfig(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(20, 20, 12, 1));

GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, 31, 15);

GPMCBaseAddrSet(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, (GPMC_DATA_BASE_ADDR >> 24));
GPMCMaskAddrSet(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, GPMC_CS_SIZE_16MB);

GPMCCSConfig(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, GPMC_CS_ENABLE);

After this configuration, I am simply trying to write to the GPMC_DATA_BASE_ADDR (we are trying to load an FPGA bitstream using CS0 as the configuration clock to the FPGA so specific address is not important).  The write instruction executes, but there is no output on the chip select or data lines.  My main concern is with the base address and mask.  From my understanding of the TRM, a write to GPMC_DATA_BASE_ADDR should put me at the first location of my configured CS0 space.  Through various trial and error, I sometimes saw a GPMC address error, though, so perhaps I am misunderstanding the base address parameter.

Also, I have verified my pinmux and clock initialization already.  Is there something further I need to configure to begin using the GPMC chip select in asynchronous 16-bit mode?

Thank you for any insight you can offer!

Nate

  • Hi,

    Can you dump the GPMC register values and post them here?
  • Hi Biser,

    Below are my GPMC register values. The device hangs when I tried to dump all GPMC registers, so I just pulled out the relevant ones. I appreciate any insight you can offer.

    GPMC_GPMC_REVISION 0x00000060
    GPMC_GPMC_SYSCONFIG 0x00000000
    GPMC_GPMC_SYSSTATUS 0x00000001
    GPMC_GPMC_IRQSTATUS 0x00000000
    GPMC_GPMC_IRQENABLE 0x00000000
    GPMC_GPMC_TIMEOUT_CONTROL 0x00001FF0
    GPMC_GPMC_ERR_ADDRESS 0x00000000
    GPMC_GPMC_ERR_TYPE 0x00000000
    GPMC_GPMC_CONFIG 0x00000B00
    GPMC_GPMC_STATUS 0x00000301
    GPMC_GPMC_CONFIG1_i_0 0x00401000
    GPMC_GPMC_CONFIG2_i_0 0x00141400
    GPMC_GPMC_CONFIG3_i_0 0x22060514
    GPMC_GPMC_CONFIG4_i_0 0x10057016
    GPMC_GPMC_CONFIG5_i_0 0x010C1414
    GPMC_GPMC_CONFIG6_i_0 0x9F0F0000
    GPMC_GPMC_CONFIG7_i_0 0x00000F41

    Thanks,
    Nate
  • Could you try with these settings:

    GPMC_GPMC_CONFIG1_i_0 0x00401000
    GPMC_GPMC_CONFIG2_i_0 0x00141400
    GPMC_GPMC_CONFIG3_i_0 0x00060602
    GPMC_GPMC_CONFIG4_i_0 0x10071007
    GPMC_GPMC_CONFIG5_i_0 0x00081414
    GPMC_GPMC_CONFIG6_i_0 0x1F000000
    GPMC_GPMC_CONFIG7_i_0 0x00000F41
  • Still no luck. I have the following code (excerpt) now:

    #define GPMC_DATA_BASE_ADDR 0x01000000

    #define GPMC_CS0_CONFIG1_REGISTER 0x50000060
    #define GPMC_CS0_CONFIG2_REGISTER 0x50000064
    #define GPMC_CS0_CONFIG3_REGISTER 0x50000068
    #define GPMC_CS0_CONFIG4_REGISTER 0x5000006C
    #define GPMC_CS0_CONFIG5_REGISTER 0x50000070
    #define GPMC_CS0_CONFIG6_REGISTER 0x50000074
    #define GPMC_CS0_CONFIG7_REGISTER 0x50000078

    #define CONFIG_REG_1_VALUE 0x00401000
    #define CONFIG_REG_2_VALUE 0x00141400
    #define CONFIG_REG_3_VALUE 0x00060602
    #define CONFIG_REG_4_VALUE 0x10071007
    #define CONFIG_REG_5_VALUE 0x00081414
    #define CONFIG_REG_6_VALUE 0x1F000000
    #define CONFIG_REG_7_VALUE 0x00000F41

    *(uint32_t *)(GPMC_CS0_CONFIG1_REGISTER) = (uint32_t)(CONFIG_REG_1_VALUE);
    *(uint32_t *)(GPMC_CS0_CONFIG2_REGISTER) = (uint32_t)(CONFIG_REG_2_VALUE);
    *(uint32_t *)(GPMC_CS0_CONFIG3_REGISTER) = (uint32_t)(CONFIG_REG_3_VALUE);
    *(uint32_t *)(GPMC_CS0_CONFIG4_REGISTER) = (uint32_t)(CONFIG_REG_4_VALUE);
    *(uint32_t *)(GPMC_CS0_CONFIG5_REGISTER) = (uint32_t)(CONFIG_REG_5_VALUE);
    *(uint32_t *)(GPMC_CS0_CONFIG6_REGISTER) = (uint32_t)(CONFIG_REG_6_VALUE);
    *(uint32_t *)(GPMC_CS0_CONFIG7_REGISTER) = (uint32_t)(CONFIG_REG_7_VALUE);

    for (i = 0; i < (bitstreamLengthBytes >> 1); i++)
    {
    *(volatile uint16_t *)(GPMC_DATA_BASE_ADDR) = ((const uint16_t *)bitstream)[i];
    }

    I even took the bistream out of it and simply tried to write 0xFFFF to GPMC_DATA_BASE_ADDR and still see no output on the chip select line. Is my use of the base address correct?

    Thanks,
    Nate
  • What software are you using?
  • I have CCS version 6.2.0.00050 and SDK version 3.01.00.06. I am using Linaro compiler v4.9.3 to run on the arm core.
  • I am just trying to run on baremetal as a starting point.
  • How do you initialize the device? I'm afraid we don't have baremetal support for this device. The RTOS SDK is the closest to baremetal we have.
  • I am initializing through custom gel files. I have been able to get all of our other peripherals (QSPI/UART/GPIO/eMMC) running fairly easily on baremetal. I don't see what would be different about the GPMC. I am still initializing all clocks and pinmuxing through the Board_init function.
  • I have asked the software team to look at this thread. They will respond directly here.
  • Hi Nate,

    Can you share what your
    GPMCBaseAddrSet(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, (GPMC_DATA_BASE_ADDR >> 24));
    and
    GPMCMaskAddrSet(GPMC_REGISTER_BASE_ADDR, GPMC_CHIP_SELECT_0, GPMC_CS_SIZE_16MB);
    functions look like?

    You can take a reference for the cs memconfig from the linux driver (drivers/memory/omap-gpmc.c from latest SDK03.01) fuincion:
    static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
    {
    u32 l;
    u32 mask;

    /*
    * Ensure that base address is aligned on a
    * boundary equal to or greater than size.
    */
    if (base & (size - 1))
    return -EINVAL;

    base >>= GPMC_CHUNK_SHIFT;
    mask = (1 << GPMC_SECTION_SHIFT) - size;
    mask >>= GPMC_CHUNK_SHIFT;
    mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;

    l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
    l &= ~GPMC_CONFIG7_MASK;
    l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
    l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
    l |= GPMC_CONFIG7_CSVALID;
    gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);

    return 0;
    }

    Where, as per device tree settings CS is 0, base is 0x08000000 and size is 0x01000000.
    And from drivers/memory/omap-gpmc.c:
    #define GPMC_CHUNK_SHIFT 24 /* 16MB */
    #define GPMC_SECTION_SHIFT 28 /* 128 MB */
    #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
    #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
    #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
    #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
    GPMC_CONFIG7_CSVALID_MASK | \
    GPMC_CONFIG7_MASKADDRESS_MASK)

    Also can you share the initialization (PRCM settings & pinmux settings) sequence for the gpmc?

    Best Regards,
    Yordan
  • Hi Yordan,

    Thank you for your suggestions. I ended up getting this to work. While replying to your post, I realized that my pinmux was not actually being configured due to the commented out "#define GPMC_ASYNC" at the top of the pin-mux tool generated file, boardPadDelayTune.h.

    It wasn't real clear (without stepping through the boardPadDelayInit.c file) that anything needed to be modified from what the pinmux tool generates.

    Anyway, once I un-commented that define, my original program works as expected.

    Thanks to everyone for your assistance,

    Nate
  • Hi Nate, 

    Thanks for updating the thread. 

    Best Regards, 
    Yordan