AM572x USB3.0 Spread Spectrum Clocking

Michi Yama

Guru 10030 points

Other Parts Discussed in Thread: AM5728

Hi,

I have one question regarding USB3.30 SSC( Spread Spectrum Clocking ).

According to the USB3 PHY Subsystem section of TRM of AM5728, it is written in the below.

The SSC can be enabled and disabled by asserting the
DPLLCTRL_USB_OTG_SS.PLL_SSC_CONFIGURATION1[0] EN_SSC bit.

For enable SSC of USB3, is only set the EN_SSC bit? Is there any special sequence?

Please let me know.

Best regards,

Michi

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

The USB experts have been notified. They will respond here.

0 Biser Gatchev-XID over 9 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

Hi,

Please see at the beginning of page 6960 in the AM572x TRM Rev. G. You need to program the SSC parameters before enabling the SSC.

0 Michi Yama over 9 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Dear Biser-san,

Thank you for your support.

Please check the below register setting.

Required spec.
* SSC enabled
* 30 kHz ~ 33kHz, 0 ~ -0.5 % changing
* REFCLK=20 MHz

Register setting value for the above required spec.
* PLL_SSC_CONFIGURATION1 register : 0x0000 0005 (2bit, 0bit = 1)
* PLL_SSC_CONFIGURATION2 register : 0x09B3 0A3D

I appreciate your quick reply.

Best regards,
Michi

0 Biser Gatchev-XID over 9 years ago in reply to Michi Yama

TI__Guru**** 393215 points

The register settings are explained at the beginning of page 6960 in the AM572x TRM Rev. G. If you followed the TRM guidelines you should be OK.

0 Michi Yama over 9 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Dear Biser-san,

Thank you for your reply.

i already read page 6960 you pointed out. But I can't understand its explanation.
This register setting is decided by our customer. But customer also does not have confidence regarding this setting.
Please give me more advice.

Best regards,
Michi

0 Biser Gatchev-XID over 9 years ago in reply to Michi Yama

TI__Guru**** 393215 points

I have asked the factory team to look at this. They will respond here.

0 Michi Yama over 9 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Dear Biser-san,

I would like to confirm some points of SSC register setting. Please forward this mal to your factory team.

My understanding of PLL_SSC_CONFIGURATION2 register is the below.

Then, MODFREQDIVIDER bit field is for moduration frequency. And DELTAM bit field is for moduration ratio.

Is my understanding right?

When customer requires the below,

Required spec.
* SSC enabled
* 30 kHz ~ 33kHz, 0 ~ -0.5 % changing
* REFCLK=20 MHz

In ths case, how do I configure the register setting? The below is right?

MODFREQDIVIDER bit field : 33000

DELTAM bit field : 0.05

Also PLL_SSC_CONFIGURATION1 register [2] Downspread bit field : 0x1

Then, the below is customer's register configuration. These setting is right?

* PLL_SSC_CONFIGURATION1 register : 0x0000 0005 (2bit, 0bit = 1)
* PLL_SSC_CONFIGURATION2 register : 0x09B3 0A3D

Please advise me.

Best regards,

Michi

0 Biser Gatchev-XID over 9 years ago in reply to Michi Yama

TI__Guru**** 393215 points

I have notified them and also sent a reminder just now.

0 Michi Yama over 9 years ago in reply to Biser Gatchev-XID

Guru 10030 points

Hi,
I am still waiting to get some advices from here.
Please reply me asap.

I appreciate your support.

Best regards,
Michi

0 Biser Gatchev-XID over 9 years ago in reply to Michi Yama

TI__Guru**** 393215 points

Sorry for the delay. I have escalated the request.

0 Y. Yang over 9 years ago

TI__Expert 4005 points

Michi-san,

Your PLL_SSC_CONFIGURATION1 register looks correct.

I need to know your M and N values to verify your PLL_SSC_CONFIGURATION2 register.

Thanks!

0 Michi Yama over 8 years ago in reply to Y. Yang

Guru 10030 points

Dear Y.Yang-san,

Thank you for your support, and sorry for my delayed reply.

I just got the PLL_SSC_CONFIGURATION2 register information from my customer.
Please see the below.

0x4A08 4C0C [20:9]bit PLL_REGM 0x4E2 ( 1250 dec.)
0x4A08 4C0C [0x9] bit PLL_REGN 0x9

I appreciate your quick reply.

Best regards,
Michi

0 Michi Yama over 8 years ago in reply to Michi Yama

Guru 10030 points

Dear Y.Yang-san,

Than you for your support.

I am waiting to receive your feedback. Please give me your advice soon.
My customer does not have enough time.

Best regards,
Michi

0 Rogerio Almeida over 8 years ago in reply to Michi Yama

TI__Mastermind 26215 points

Michi,
Thanks for your post...our apps will take a look...as you know, most of us took some time off between holidays and your response came during holidays, so I am expecting apps would be replying soon...

0 Y. Yang over 8 years ago in reply to Michi Yama

TI__Expert 4005 points

Michi,

Can you ask your customer how they calculated the value they put into the register (9b30A3D)?

Doing the calculations on our side it appears the correct value for what they want to do should be 0x0800C800.

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AM572x USB3.0 Spread Spectrum Clocking