AM335X: ADC Opendelay and Sampledelay

Börje Sewing

Other Parts Discussed in Thread: AM3352

Hi,

i am using the adc of an AM3352 SoC as a general purpose adc for measuring sensor data. The customer specific boards runs with linux, kernel version is mainline 3.18 with backported tscadc-driver, tested with mainline kernel 4.8 as well.

The adc is configured in the dts as follows:

adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
ti,chan-step-opendelay = <0xf00 0xf00 0xf00 0xf00 0xf00 0xf00 0xf00 0xf00>;
ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
ti,chan-step-avg = <16 16 16 16 16 16 16 16>;
};

There occur measurement errors if i lower the opendelay values, especially at channel 0. What values do i have to set for opendelay and sampledelay? Is it necessary to set the same values for every channel?

Thanks in advance!

Börje

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

Neither of these kernels is an official TI release. You can download the TI released AM335x Linux SDK here: www.ti.com/.../PROCESSOR-SDK-AM335X Additional information can be found here: processors.wiki.ti.com/.../Processor_SDK_Linux_ADC

0 Börje Sewing over 8 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hi Biser,

i tested the kernel from the TI Linux SDK (4.4.19-gdb0b54cdad #1 Tue Nov 1 12:43:00 UTC 2016 armv7l GNU/Linux), just added a board specific dts file. Same issue here.

What are valid values for opendelay and sampledelay? Is it necessary to set the same values for every channel?

Regards,
Börje

0 Yordan Kovachev over 8 years ago in reply to Börje Sewing

TI__Guru**** 161600 points

Hi Börje,

What are valid values for opendelay and sampledelay?

I am afraid that I couldn't find a straight forward answer to your question. You should experiment with the values and reside with the ones that match your use case.

Have a look at Section 12.3.2 Open Delay and Sample Delay: The sample delay is the time between driving the inputs to the AFE and the time to send the start of conversion signal. It can be used to allow the the voltages to stabilize before sampling. And the sample delay is actually the sampling (width of the of the start of conversion signal).

Is it necessary to set the same values for every channel?

No, there is no such requirement. You can set every channel with different open delay & sample delay, this depends on your use case.

Best Regards,
Yordan

0 Börje Sewing over 8 years ago in reply to Yordan Kovachev

Prodigy 150 points

Hi Yordan,

we have the problem that adc channel 0 and channel 1 crosstalk. After setting open delay and sample delay to their max values (via DTS file), the problem still exists.

Are maximum values for open and sample delays not the best (but slowest) values?

Best Regards,
Börje

0 peaves over 8 years ago in reply to Börje Sewing

TI__Guru 62855 points

Open Delay and Sample Delay
The FSM sequencer provides two programmable delays for each step. Open Delay is used to control when the acquisition begins after the step starts and Sample Delay is used to control the acquisition period. Delays for each of the 16 steps can be configured independently via the respective STEPDELAYx register.

Open Delay
Open Delay defaults to a value of zero which causes the acquisition period to begin as soon as the step starts. The start of the acquisition period can be delayed one adc_clk clock period for each incremental value of Open Delay.

Sample Delay
Sample Delay defaults to a value of zero which causes the acquisition period to be equal to two adc_clk clock periods. The acquisition period can be extended one adc_clk clock for each incremental value of Sample Delay. The value of Sample Delay should be configured to provide enough time for the respective external voltage source to completely charge the AFE input capacitance during the acquisition period.

Regards,
Paul

0 Börje Sewing over 8 years ago in reply to peaves

Prodigy 150 points

Dear Paul,

thanks, i read the cited paragraphs in the AM437x ARM ® Cortex™-A9 Processors TRM. Actually i already read the whole chapter. Still no clue what the problem could be.

What about default values from other boards (such as Ti AM33xx and AM43xx eval boards) or maybe a rule of thumb if the adc is used as general purpose adc?

Best Regards,
Börje

0 peaves over 8 years ago in reply to Börje Sewing

TI__Guru 62855 points

The Open Delay is a synchronous delay based on the adc_clk. This delay allows the user to insert fixed delays between steps when they need the ADC to sample at very predictable periodic sample rates that falls between the rate adjustment provided by changing the adc_clk divider. This delay does not have any effect on accuracy of the acquisition.

Sample Delay does effect accuracy of the acquisition. This delay determines how long the sample and hold capacitor in the ADC is connected to your source. So the accuracy is a function of your source impedance, the value of the ADC sample and hold capacitor, and the time you allow your source to charge the capacitor. The ADC sample and hold capacitor has a typical value of 5.5pf. You should determine the impedance of your source and use this value to calculate how long it takes to fully charge the 5.5pf sample and hold capacitor. The recommendation is to allow enough time for the capacitor to charge within 25% of one LSB of the applied voltage. For example, the capacitor should be given enough time to charge to within 440uV of the applied voltage if your ADC is configured to operate in single-ended mode with reference voltage of 1.8 volts.

Regards,
Paul

0 Börje Sewing over 8 years ago in reply to peaves

Prodigy 150 points

Thanks Paul,

for those of you out there who have similar problems: it's a software problem and has been fixed in linux kernel with following commit:

90c43ec6997a892448f1f86180a515f59cafd8a3
iio: adc: ti_am335x_adc: Protect FIFO1 from concurrent access

Regars,
Börje

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AM335X: ADC Opendelay and Sampledelay