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36 bit DDR3 interfacing with K2L

Sreejaya Varma
Intellectual 430 points

Hi,

In our new design with K2L processor,due to space constraints, we are planning to use the DDR3 memory controller interface in 36bit - Three 16bit SDRAMs (including 4 bits of ECC) -configuration. Evaluation board has 72 bit configuration only.So there is some confusion regarding the connection of LDM/UDM and LDQS/UDQS to the ECC  SDRAM.
Below is the connection diagram between K2L and SDRAMs. Please review it and comment if I have gone wrong.

Regards

Sreejaya

  • 0
    TI__Guru 65405 points
    Hi Sreejaya,

    I've forwarded this to the DDR experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Mastermind 42545 points

    Hi Sreejaya,

    I'm not seeing the diagram. Can you try and post it again or attach it as a file?

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    Intellectual 430 points
    Hi Tsvetolin Shulev/Bill,
    I have added the connection diagram.Please go through it.

    Regards
    Sreejaya
  • 0 in reply to Sreejaya Varma
    TI__Mastermind 42545 points

    Hi Sreejaya,

    In the diagram, you are connecting DM4 and DQS4P/N to the check byte memory. This is not correct. DM8 and DQS8P/N should be used for this byte. You should check with the memory manufacturer to determine what you should do with the unused data bits on the memory.

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    Intellectual 430 points
    Hi Bill,
    Thank you for the inputs.

    In the datasheet of the 16 bit ddr sdram, in the case of using only one byte(8 bits) , connection of upper byte is given as below.

    • A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be
    used, use the lower byte for data transfers and terminate the upper byte as noted:
    – Connect UDQS to ground via 1kΩ resistor.
    – Connect UDQS# to VDD via 1kΩ resistor.
    – Connect UDM to VDD via 1kΩ resistor.
    – Connect DQ[15:8] individually to either VSS, VDD, or VREF via 1kΩ resistors, or float
    DQ[15:8].

    But in the EVM ECC SDRAM,
    - UDQS is connected to VDD via resistor.
    - UDQS# is connected to ground via resistor.
    - UDM to ground via resistor
    - DQ[15:8] to ground.
    Why is it so?

    Also, if only 4 ECC bits are to be used out of 8 (in 36 bit configuration),
    - should we connect all 8 bits to SDRAM and the masking of the high side four bits will be taken care by the DDR3 controller or
    - we should connect only 4 bits ( DQ0 - ECC3,DQ2 - ECC2,DQ5 - ECC0,DQ7 - ECC7 as in EVM) and others left unconnected?

    Also should we connect ECC in the same order as data bits are shuffled?

    Is there any specific documentation describing the shuffling of data bits of SDRAM?

    Regards
    Sreejaya
  • 0 in reply to Sreejaya Varma
    TI__Mastermind 42545 points

    Hi Sreejaya,

    I didn't design the K2L EVM  but I'm assuming that the engineer was working with the best information that he had at that time. The signals are terminated so that they won't be toggling, which is the primary goal. I would use the information provided by the DRAM manufacturer.

    You don't need to connect all eight of the ECC bits since only four are used but you must connect ECC0-ECC3. If you choose to connect these bits to others on the SDRAM, be sure to terminate the unused bits. There isn't any specific information on bit shuffling, most has been provided through E2E. Generally, a DDR3 memory will use the least significant bit of a byte for leveling purposes. The TI DDR3 controller checks all the bits in case the LSb has been shuffled to a different bit location. Bit shuffling can be different from byte to byte. There is no requirement that the shuffling be consistent.

    Regards,

    Bill