Hello!
I'm trying ROM SPI boot example and at first I've loaded prebuilt images due to docs in project directory. I've used norwriter_evm6678.out and app.data from writer dir and loaded GEL-file from MCSDK_2_01_02_06. After running norwriter and power up board I see no led blinking. Also after loading GEL-file there was only messages in console describing that Setup_Memory_Map... Done. In doc I see a lot of other messages in picture. What's wrong with loading GEL-file could it be?
Alex,
I tried the prebuilt boot binary on the EVM and I am able to blink the LEDs as described int he document. Based on your inputs let me try to debug your setup and see if that helps root cause the issue:
1. Initially when you powered up the EVM, did you set the switch to no boot mode.
2. When you connect to the target to flash the device, did you use the C6678 GEL file while creating the target configuration file in CCS.
when you connect to the device, you should see a GEL initialization log as shown below:
C66xx_0: GEL Output: Connecting Target... C66xx_0: GEL Output: DSP core #0 C66xx_0: GEL Output: C6678L GEL file Ver is 2.00500011 C66xx_0: GEL Output: Global Default Setup... C66xx_0: GEL Output: Setup Cache... C66xx_0: GEL Output: L1P = 32K C66xx_0: GEL Output: L1D = 32K C66xx_0: GEL Output: L2 = ALL SRAM C66xx_0: GEL Output: Setup Cache... Done. C66xx_0: GEL Output: Main PLL (PLL1) Setup ... C66xx_0: GEL Output: PLL in Bypass ... C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz. C66xx_0: GEL Output: SYSCLK2 = 333.333344 MHz, SYSCLK5 = 200.0 MHz. C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz. C66xx_0: GEL Output: PLL1 Setup... Done. C66xx_0: GEL Output: Power on all PSC modules and DSP domains... C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done. C66xx_0: GEL Output: PA PLL (PLL3) Setup ... C66xx_0: GEL Output: PA PLL Setup... Done. C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... C66xx_0: GEL Output: DDR3 PLL Setup... Done. C66xx_0: GEL Output: DDR begin (1333 auto) C66xx_0: GEL Output: XMC Setup ... Done C66xx_0: GEL Output: DDR3 initialization is complete. C66xx_0: GEL Output: DDR done C66xx_0: GEL Output: DDR3 memory test... Started C66xx_0: GEL Output: DDR3 memory test... Passed C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ... C66xx_0: GEL Output: configSGMIISerdes Setup... Begin C66xx_0: GEL Output: SGMII SERDES has been configured. C66xx_0: GEL Output: Enabling EDC ... C66xx_0: GEL Output: L1P error detection logic is enabled. C66xx_0: GEL Output: L2 error detection/correction logic is enabled. C66xx_0: GEL Output: MSMC error detection/correction logic is enabled. C66xx_0: GEL Output: Enabling EDC ...Done C66xx_0: GEL Output: Configuring CPSW ... C66xx_0: GEL Output: Configuring CPSW ...Done C66xx_0: GEL Output: Global Default Setup... Done. C66xx_0: GEL Output: Invalidate All Cache... C66xx_0: GEL Output: Invalidate All Cache... Done. C66xx_0: GEL Output: GEL Reset... C66xx_0: GEL Output: GEL Reset... Done. C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.
3. You are correct, after you load the pre-built app.dat in the package, you need to change the 8th word from 0x5100f401 to 0x0000f401
4. When the SPI writer completes, you should see the following console message
[C66xx_0] NOR Writer Utility Version 01.00.00.03 Flashing sector 0 (0 bytes of 58860) Reading and verifying sector 0 (0 bytes of 58860) NOR programming completed successfully
5. After the flashing is completed, please set the eVM to SPI boot as described here:
Other debug techniques:
* If the LEDs don`t blink in SPI boot. Connect to device in CCS (Remove GEL initialization before connecting). check the value of C66x_0 Program counter. If the Device is in region 0x0080xxxx that means the device is stuck in ROM. Report the PC value.
* After connecting to device and checking PC, run the debug GEL file provided here and check if the device initialization and ROM status:
Hope this helps.
Regards,
Rahul
I believe that this is the root cause of the issue for the SPI boot, the DEVSTAT register needs to be set to 0x000040D as you can see:
This means that the BOOTMODE PINS of the SOC are not being driven correctly by the FPGA on your EVM. On the EVM the FPGA drives the boot mode pins based on the SW settings and this firmware doesn`t seem to be working as expected. If this is a new EVM then, I recommend that you report the issue to the board manufacturer.
The FPGA firmware is available on Board manufacturer website here if you choose to reflash the firmware:
Before you flash the FPGA firmware, you can try the following steps to confirm SPI boot is working.e
1. Open Memory browser, go to KICK0 register (0x0262 0038) and write value 0x83E70B13
2. Got to KICK1 (0x0262003C) and write value 0x95A4F1E0; This will unlock the bootcfg Register space.
3. Now got to DEVSTAT register and change it to 0x0000040D to set SPI boot mode.
4. Now select Core0 and go to Run->Reset ->CPU Reset. This will set Core0 PC to 0x20B00000 (start of ROM)
5. Now click on Core0 and run the core (or Press F8).
Let me know if you see the LEDs blinking now.
Regards,
Rahul
Alex,
If the switches are set to SPI boot mode and you see the DEVSTAT as 0x0000080b then I think there is some hardware issue with the EVM.
The BOOTMODE[15:0] pins are latched into DEVSTAT register when you power up the SOC and as you can see from the schematics these BOOTMODE pins to the SOC are driven by the GPIOs from the FPGA on the EVM. The FPGA reads the Switch settings and then drives the GPIOs to set the BOOTMODE pins.
Can you confirm the revision number of your EVM and also that the switch settings are for ROM SPI boot as shown in the image below:
The BootROM reads the DEVSTAT to determine the boot mode and to set the PLL clocks etc.
SPI boot DEVSTAT: 0x40D (little endian SPI boot)
I2C boot DEVSTAT: 0x80B (Little endian I2C boot). This is used for IBL NOR boot not for ROM SPI boot.
Regards,
Rahul
