Hello
I have some questions about EDMA3 programming, I work on OMAPL137 and I choose to program directly the registers (without CSL or LLD). My objective is to write a transfer process (SPI0 peripheral servicing ). I have managed to program two EDMA channels. One gets DMA request from SPI0 Receive, another gets DMA request from SPI0 Transmit. I also program two EDMA channels to generate a transfer completion interrupt to DSP (the final transfer interrupt in normal completion mode). But the EDMA generates a channel controller error interrupt besides the transfer completion interrupt. The following is the EDMA channels configuration :
EDMA channel configuration for SPI0 Receive:
SPIREV_OPT = 0
| ( 0 << 2 ) // A-synchronized
| ( 0 << 3 ) // not static
| ( 0 << 1 )
| ( 0 << 0 ) // don't use the fifo
| ( 0 << 12 ) // set tcc 01
| ( 0 << 21 )
| ( 1 << 20 ) // inturup enabled, the last TR trigger interupt
| ( 1 << 8 ) // 16 BIT FIFO(not be used)
| ( 0 << 11 ); // each TR one interupt
SPIREV_SRC = 0x01C41040 ;
SPIREV_A_B_CNT = 0x00080002 ; // 8 group,16 bit
SPIREV_DST = (Uint32)Adresult;
SPIREV_LINK_BCNTRLD = 0x0008FFFF ; // link to null
SPIREV_CCNT = 0x00000001 ; // one frame, send once
SPIREV_SRC_DST_BIDX = 0x00020000 ;
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EDMA channel configuration for SPI0 Transmit:
SPITRA_OPT = 0
| ( 0 << 2 ) //A-synchronized
| ( 0 << 3 ) //not static
| ( 0 << 1 )
| ( 0 << 0 ) //don't use the fifo
| ( 1 << 12 ) //set tcc 02
| ( 0 << 21 )
| ( 1 << 20 ) //inturup enabled, the last TR trigger interupt
| ( 1 << 8 ) //16 BIT FIFO(not be used)
| ( 0 << 11 ); //each TR one interupt
SPITRA_SRC = (Uint32)&RANDOM ;
SPITRA_A_B_CNT = 0x00080002 ;//8 group,16 bit
SPITRA_DST = 0x01C4103C;
SPITRA_LINK_BCNTRLD = 0x0008FFFF; // link to null
SPITRA_CCNT = 0x00000001 ; //one frame, send once
SPITRA_SRC_DST_BIDX = 0x00000000 ;
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In my program, I make the CPU to wait for the corresponding bit in IPR(EDMA3) being set. As long as the corresponding bit in IPR(EDMA3) is set, the DMA request is disable in the SPIINT0 bit and the SPI0 Receive and Transmit Event is disable in the EECR bit. Here is the code :
while( (EDMA3CC_IPR & 0x0000003) != 3 );
SPI0_SPIINT0 = 0;
EDMA3CC_EECR = 0xFFFFFFFF;
As Mukul's mention in http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/51777.aspx, I have finished/expired a PaRAM set and had it configured to Link to NULL , so I have disabled the SPI0 peripheral sending request to the EDMA . But the EDMA still generates a channel controller error interrupt, and this confused me. I don't know whether the error interrupt can be ignored in this case. I have checked the EDMA3CC error registers, the EMR is 0x00008000 and the rest are 0x00000000, which implies that there is a SPI0 Transmit Event missed.
Regards
Liang
