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AM572x bug in PDK 1.0.4 PCIe example

Tim Dylla
Expert 1070 points
Other Parts Discussed in Thread: AM5728

Hi,

  I'm trying to comprehend the BAR cfg part of the PCIe example of the said RTOS PDK package on an am5728EVM.

There is a function pcieCfgDbi(Pcie_Handle handle, uint8_t enable) (pcie_sample:380) that is misleading to say the least. 

It is supposed to set certain PCIe registers RW/RO via DIF. But the enable parameter is never used. It always sets the registers RO.

Since in the example the enable parameter is set to 1 and I interpert that as 'enable read/write' I wonder why the example still seem to work.

Best,

              Tim

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points

    Tim,

    AM5728 is HW-Rev1, for that function:

    pcieRet_e pcieCfgDbi(Pcie_Handle handle, uint8_t enable)
    {
      pcieRegisters_t        regs;
      pcieRet_e              retVal;
    #ifdef PCIE_REV0_HW
      .....
    #else
      pciePlconfDbiRoWrEnReg_t dbiRo;

      memset (&dbiRo, 0, sizeof(dbiRo));
      memset (&regs, 0, sizeof(regs));

      regs.plconfDbiRoWrEn = &dbiRo;

      if ((retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
      {
        PCIE_logPrintf ("SET CMD STATUS register failed!\n");
        return retVal;
      }
    #endif
      return pcie_RET_OK;
    } /* pcieCfgDbi */

    So regardless enable is 0 and 1, we always memset (&dbiRo, 0, sizeof(dbiRo)); and write 0 to this register PCIECTRL_PL_DBI_RO_WR_EN. This is not a PCIE write over DIF, but a local write. Check AM572x TRM 24.9.4.8.2 PCIe Configuration Type (Cfg) Traffic Management, why we need to set this to 0.

    For different HW, we want to keep the API the same. pcieRet_e pcieCfgDbi(Pcie_Handle handle, uint8_t enable). For HW REV0, it is for Keystone I and II PCIE, what passed from "enable" need to be programed to CMD STATUS register. For HW REV1, it is for AM57x PCIE, what passed from "enable" doesn't matter, it always write 0 to PCIECTRL_PL_DBI_RO_WR_EN.

    Regards, Eric 

     

  • 0 in reply to lding
    Expert 1070 points

    Haha,

      sure, this explains it all...

    Thanxalot,

           Tim