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Keystone 2 EMIF16: Is a 32-bit transaction "atomic" on the external interface?

Gerald Ruescher
Intellectual 300 points

We use the EMIF interface of the Keystone II to connect an external FPGA to the processor.

Our software will access the memory area of the EMIF16 interface, using standard 32 bit memory transactions (read and write).
The EMIF16 itself is only 16 bit so at some level, the 32 bit transaction has to be split into two 16 bit transactions

Now lets suppose that two CPU cores of the Keystone access the EMIF16 interface at the same time, i.e. both issue 32 bit transactions to the EMIF16

Our question is:
Is it guaranteed that a 32 bit transaction from one core will be fully completed before a transaction from another core takes place?


Example:

Core A issues a 32-bit read from address 0x3000.0000 / 32
The EMIF16 then needs to read 0x3000.0000 / 16 and 0x3000.0002 / 16

At the same time core B issues a 32-bit read from address 0x3000.FFF0 / 32
The EMIF16 then needs to read 0x3000.FFF0 / 16 and 0x3000.FFF2 / 16

Can the following happen on the EMIF16 bus?

1. read 0x3000.0000 / 16
2. read 0x3000.FFF0 / 16
3. read 0x3000.0002 / 16
4. read 0x3000.FFF2 / 16


Thanks alot!

Gerald

  • 0
    TI__Guru 65405 points
    Hi Gerald,

    I've forwarded this to the EMIF experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Guru** 116170 points
    EMIF16 peripheral has a VBUSP slave port, which only support a single pending transaction at any given time. It means when there are multiple transactions sent to EMIF25, the transactions will be serialized at the VBUSP port.

    We recommend that you use semaphores to prevent simultaneous access from multiple cores to guarantee 32 bit transaction has completed on each core.

    Regards,
    Rahul
  • 0
    Mastermind 6930 points
    Gerald,

    HI, thanks for posting this question. I have often thought of using the EMIF16 to interface to an FPGP. However, the documentation on the EMIF16 is really slanted to be used with NOR or NAND memory. So that gave me a little uneasy feeling. Also, I read a previous post a long time ago and the engineer used the EMIF to link to an FPGA and he was experiencing data transfer rates that didn't make the datasheet. With that said I thought that a better link between the TI processor and an FPGA would be to use SPI or I2C for the low speed traffic and using PCIe for the high speed traffic. This is easy for the TI processor but a little cumbersome for the FPGA programmer. I would rater have a nice parallel bus to work with like the EMIF but with more determinism. I used the TigerSharc DSP on my designs and it had a beautiful 64-bit data bus and was very easy to interface with an FPGA. But big parallel buses are being replaced with high speed serial which I'm sure you already know

    When you get this working please share your results and comments. I'd like to know how well it worked out and if you would recommend this approach to other.

    Thanks,
    Joe
  • 0 in reply to joe lindula
    Intellectual 300 points

    Joe,

    yes, we will share our experiences. In our application, throughput is not so much an issue but latency is.  Our software needs to issue few 32-bit read and write accesses to HW, but when it does, we need the lowest latency possible. Using PCIe is not an option here due to the internal protocol overhead so we need to stick to a parallel bus (which seems to be a dying technology when it comes to SoCs wich high-performance CPU cores).

    Cheers,
    Gerald

  • 0 in reply to Rahul Prabhu
    Intellectual 300 points

    Rahul,

    thanks for your answer.

    Are sure that this really can happen?  Let's take a look at the HW diagram from the Keystone spec:

    So let's assume 2 CPU cores issue a 32-bit read transacation each (at the same time). I'd expect that a 32-bit transactions is"atomic" on the TeraNet switch and thus should be properly serialized the interfaces which lead to the EMIF16.

    Which hardware instance would be responsible for transforming this into a sequence of 4 interleaved 16 bit transactions?

  • 0 in reply to Gerald Ruescher
    Intellectual 300 points

    The diagram somehow got lost in my lastt post