Xclkfail in xstat is set automatic after clear also.

1. I am trying to write my own bare metal driver code for Beagle Bone Black B6 board. i am getting transmit clock failure that is XCLKFAIL bit in XSTAT. so i configure XCLKHK register, by following the below steps

It is expected, initially, that the clock-failure circuits will generate an error until at least one measurement
has been taken. Therefore, the clock failure interrupts, clock switch, and mute functions should not
immediately be enabled, but be enabled only after a specific startup procedure. The startup procedure is:
1. For the transmit clock failure check:
(a) Configure transmit clock failure detect logic (XMIN, XMAX, XPS) in the transmit clock check control
register (XCLKCHK).
(b) Clear transmit clock failure flag (XCKFAIL) in the transmit status register (XSTAT).
(c) Wait until first measurement is taken (> 32 AHCLKX clock periods).
(d) Verify no clock failure is detected.
(e) Repeat steps b–d until clock is running and is no longer issuing clock failure errors.
(f) After the transmit clock is measured and falls within the acceptable range, the following may be
enabled:
(i) transmit clock failure interrupt enable bit (XCKFAIL) in the transmitter interrupt control register
(XINTCTL).
(ii) transmit clock failure detect autoswitch enable bit (XCKFAILSW) in the transmit clock check
control register (XCLKCHK).
(iii) mute option (XCKFAIL) in the mute control register (AMUTE).


so i configure xclkchk register as follow

xmax = 0xff;
xmin = 0x00;
xps = 0x08

MCASP_XCLKCHK = 0x00FF0008;


if(REGR32_FIELD(MCASP_XSTAT,XCKFAIL) == 1){
MCASP_XSTAT = 0x0000FFFF;
MCASP_XINTCTL = 0x00000000
}

while(1){
if(REGR32_FIELD(MCASP_XCLKCHK,XCNT) > 32)
break;

if(REGR32_FIELD(MCASP_XSTAT,XCKFAIL) == 1){
REGW32(MCASP_XSTAT,0x0000FFFF);
REGW32(MCASP_XINTCTL,0x00000000);
}
}


2. i want to test this driver in loop back mode.

Wait until first measurement is taken (> 32 AHCLKX clock periods).
is it mean XCNT > 32 or what?

HI Sir,

Thank you for the response

i am checking the XCNT field but it is not changing it is zero only, here i am attaching the my driver code please tell me where i did the mistake

/*!
 * \brief Read data from the audio interface FIFO register. This routines takes
sample_sz as input argument which is in bits
* \param[out] buf
* \param[in] len
* \param[in] serilizer_no
* \param[in] sample_sz
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */



static int device_read(char *buf,
                unsigned int len,
                unsigned int serilizer_no,
                unsigned int sample_sz,
                struct mcasp_prv_data *pdata)
{
    unsigned short u16_sample;
    unsigned int count;
    unsigned int varrbufserilizer_no;

    /* Sample width 8 bits */
    if (sample_sz == 8) {
        count = 0;
        while (count < len) {
            varrbufserilizer_no = REGR32(MCASP_RBUF + 4 * (serilizer_no - 0));
            buf[count] = varrbufserilizer_no;
            count++;
        }
    }

    /* Sample width 16 bits  */
    if (sample_sz == 16) {
        count = 0;
        while (count < len) {
            varrbufserilizer_no = REGR32(MCASP_RBUF + 4 * (serilizer_no - 0));
            u16_sample = varrbufserilizer_no;
            buf[count] = (char) (u16_sample & 0xff);
            count++;
            buf[count] = (u16_sample >> 8) & 0xff;
            count++;
        }
    }

    return Y_SUCCESS;
}


/*!
 * \brief Write data to audio interface FIFO register. This routines takes
sample_sz as input argument which is in bits
* \param[in] buf
* \param[in] len
* \param[in] serilizer_no
* \param[in] sample_sz
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */



static int device_write(char buf[],
                unsigned int len,
                unsigned int serilizer_no,
                unsigned int sample_sz,
                struct mcasp_prv_data *pdata)
{
    unsigned short u16_sample;
    unsigned int count;

    /* Sample width 8 bits  */
    if (sample_sz == 8) {
        count = 0;
        while (count < len) {
            REGW32(MCASP_XBUF + 4 * (serilizer_no - 0), buf[count]);
            count++;
        }
    }

    /* Sample width 16 bits */
    if (sample_sz == 16) {
        count = 0;
        while (count < len) {
            u16_sample = 0;
            u16_sample = (unsigned short) (buf)[count];
            count++;
            u16_sample = u16_sample | (buf[count] << 8);
            count++;
        
            REGW32(MCASP_XBUF + 4 * (serilizer_no - 0), u16_sample));
        }
    }

    return Y_SUCCESS;
}




/*!
* \brief Initialises device registers.
* \details This function initialises device registers.
*
* \return none
 */

int mcasp_yinit(struct mcasp_prv_data *pdata)
{

    REGW32_FIELD(MCASP_CM_PER_MCASP0_CLKCTRL, MODULEMODE, 0x2);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_CM_PER_MCASP0_CLKCTRL, IDLEST) == 0)
            break;    
    }

    REGW32(MCASP_GBLCTL, 0);
 
    REGW32(MCASP_XSTAT,0x0000FFFF);
    REGW32(MCASP_RSTAT,0x0000FFFF);
    REGW32(MCASP_XINTCTL,0x00000000);   
    REGW32_FIELD(MCASP_PWRIDLESYSCONFIG, IDLEMODE, 1);
    REGW32(MCASP_WFIFOCTL, 0x10101);
    REGW32(MCASP_RFIFOCTL, 0x10101);

    return Y_SUCCESS;
}




/*!
* \brief Exit routine.
* \details Exit function that unregisters the device, deallocates buffers,
    unbinds the driver from controlling the device etc..
*
* \return Returns successful execution of the routine
* \retval Y_SUCCESS Function executed successfully
 */


int mcasp_yexit(struct mcasp_prv_data *pdata)
{

    REGW32(MCASP_GBLCTL, 0);
    REGW32(MCASP_PFUNC, 0xffffffff);
    REGW32(MCASP_PDIR, 0);
    REGW32(MCASP_XSTAT, 0xffffffff);
    REGW32(MCASP_RSTAT, 0xffffffff);

    return Y_SUCCESS;
}




/*!
 * \brief configuration for loop back mode
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */

static int loopback(struct mcasp_prv_data *pdata)
{

    REGW32_FIELD(MCASP_DLBCTL, DLBEN, 1);
    REGW32_FIELD(MCASP_DLBCTL, ORD, 1);
    REGW32_FIELD(MCASP_DLBCTL, LOOPBACK_MODE, 1);
    REGW32_FIELD(MCASP_ACLKXCTL, ASYNC, 0);

    return Y_SUCCESS;
}




/*!
 * \brief Set bit clock and frame clock properties like polarity,
master/slave, gated/continuous
This sequence is mandatory for only for I2S phy type.
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */

static int clock_settings_rx(struct mcasp_prv_data *pdata)
{
    struct s_DEVICE_CONFIG *device_config = GET_DEVICE_CONFIG_PTR;
    unsigned int varmaster_slave;
    unsigned int varpol;

    GET_BITS(DEVICE_CONFIG_CLOCK_MASTER_SLAVE_HBIT_POS, DEVICE_CONFIG_CLOCK_MASTER_SLAVE_LBIT_POS, device_config->CLOCK, varmaster_slave);
    if (varmaster_slave == DEVICE_CONFIG_CLOCK_MASTER_SLAVE_BIT_CLKM_FRAME_CLKM) {
        REGW32_FIELD(MCASP_AFSRCTL, FSRM, 1);
        REGW32_FIELD(MCASP_ACLKRCTL, CLKRM, 1);
        REGW32_FIELD(MCASP_AHCLKRCTL, HCLKRM, 1);
    } else if (varmaster_slave == DEVICE_CONFIG_CLOCK_MASTER_SLAVE_BIT_CLKS_FRAME_CLKS) {
        REGW32_FIELD(MCASP_AFSRCTL, FSRM, 0);
        REGW32_FIELD(MCASP_ACLKRCTL, CLKRM, 0);
        REGW32_FIELD(MCASP_AHCLKRCTL, HCLKRM, 0);
    }

    GET_BITS(DEVICE_CONFIG_CLOCK_POL_HBIT_POS, DEVICE_CONFIG_CLOCK_POL_LBIT_POS, device_config->CLOCK, varpol);
    if (varpol == DEVICE_CONFIG_CLOCK_POL_BIT_CLKNP_FRAME_CLKNP) {
        REGW32_FIELD(MCASP_ACLKRCTL, CLKRP, 1);
        REGW32_FIELD(MCASP_AFSRCTL, FSRP, 1);
    } else if (varpol == DEVICE_CONFIG_CLOCK_POL_BIT_CLKIP_FRAME_CLKNP) {
        REGW32_FIELD(MCASP_ACLKRCTL, CLKRP, 0);
        REGW32_FIELD(MCASP_AFSRCTL, FSRP, 1);
    }

    return Y_SUCCESS;
}




/*!
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */

static int clock_settings_tx(struct mcasp_prv_data *pdata)
{
    struct s_DEVICE_CONFIG *device_config = GET_DEVICE_CONFIG_PTR;
    unsigned int varmaster_slave;
    unsigned int varpol;

    GET_BITS(DEVICE_CONFIG_CLOCK_MASTER_SLAVE_HBIT_POS, DEVICE_CONFIG_CLOCK_MASTER_SLAVE_LBIT_POS, device_config->CLOCK, varmaster_slave);
    if (varmaster_slave == DEVICE_CONFIG_CLOCK_MASTER_SLAVE_BIT_CLKM_FRAME_CLKM) {
        printf("varmaster_slave : %u\n",varmaster_slave);
        REGW32_FIELD(MCASP_AFSXCTL, FSXM, 1);
        REGW32_FIELD(MCASP_ACLKXCTL, CLKXM, 1);
        REGW32_FIELD(MCASP_AHCLKXCTL, HCLKXM, 1);
        printf("AHCLKXCTL : %x\n",REGR32(MCASP_AHCLKXCTL));
        printf("FSXM : %x\n",REGR32_FIELD(MCASP_AFSXCTL, FSXM));
    } else if (varmaster_slave == DEVICE_CONFIG_CLOCK_MASTER_SLAVE_BIT_CLKS_FRAME_CLKS) {
        REGW32_FIELD(MCASP_AFSXCTL, FSXM, 0);
        REGW32_FIELD(MCASP_ACLKXCTL, CLKXM, 0);
        REGW32_FIELD(MCASP_AHCLKXCTL, HCLKXM, 0);
    }

    GET_BITS(DEVICE_CONFIG_CLOCK_POL_HBIT_POS, DEVICE_CONFIG_CLOCK_POL_LBIT_POS, device_config->CLOCK, varpol);
    if (varpol == DEVICE_CONFIG_CLOCK_POL_BIT_CLKNP_FRAME_CLKNP) {
        REGW32_FIELD(MCASP_ACLKXCTL, CLKXP, 1);
        REGW32_FIELD(MCASP_AFSXCTL, FSXP, 1);
    } else if (varpol == DEVICE_CONFIG_CLOCK_POL_BIT_CLKIP_FRAME_CLKNP) {
        REGW32_FIELD(MCASP_ACLKXCTL, CLKXP, 0);
        REGW32_FIELD(MCASP_AFSXCTL, FSXP, 1);
    }

    return Y_SUCCESS;
}




/*!
 * \brief Set hardware properties
play_back: 0 - capture
1 - playback
num_chnls: Number of playback/capture channels
frm_rate: Frame rate
* \param[in] num_chnls
* \param[in] serilizer_no
* \param[in] frm_rate
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
*/


static int set_hw_params_tx(unsigned int num_chnls,
                unsigned int serilizer_no,
                unsigned int frm_rate,
                struct mcasp_prv_data *pdata)
{
    unsigned int bit_rate, i =0;
    unsigned int bit_per_frame = 0;
     unsigned char clk_div;
    struct s_DEVICE_CONFIG *device_config = GET_DEVICE_CONFIG_PTR;
    unsigned long varbit_formats;

    REGW32_FIELD(MCASP_XFMT, XROT, 0);
    REGW32_FIELD(MCASP_XFMT, XBUSEL, 1);
    REGW32_FIELD(MCASP_XFMT, XRVRS, 1);
    REGW32_FIELD(MCASP_XFMT, XDATDLY, 1);

    clock_settings_tx(pdata);

    GET_BITS(DEVICE_CONFIG_PCM_BIT_FORMATS_BIT_FORMATS_HBIT_POS, DEVICE_CONFIG_PCM_BIT_FORMATS_BIT_FORMATS_LBIT_POS, device_config->PCM_BIT_FORMATS, varbit_formats);
    if (varbit_formats == DEVICE_CONFIG_PCM_BIT_FORMATS_BIT_FORMATS_PCM_FORMAT_S16_LE) {
        REGW32_FIELD(MCASP_XFMT, XSSZ, 7);
        bit_per_frame = 16;
    } else if (varbit_formats == DEVICE_CONFIG_PCM_BIT_FORMATS_BIT_FORMATS_PCM_FORMAT_U8) {
        REGW32_FIELD(MCASP_XFMT, XSSZ, 3);
        bit_per_frame = 8;
    }

    REGW32_FIELD(MCASP_AFSXCTL, FXWID, 1);
    REGW32_FIELD(MCASP_AFSXCTL, XMOD, num_chnls);
    bit_rate = bit_per_frame * frm_rate;
    clk_div = 26000000 / bit_rate;
    REGW32_FIELD(MCASP_ACLKXCTL, CLKXDIV, clk_div - 1);
    printf("CLKXDIV : %x\n",REGR32_FIELD(MCASP_ACLKXCTL, CLKXDIV));
    REGW32_FIELD(MCASP_AHCLKXCTL, HCLKXDIV, 0);
    REGW32(MCASP_XTDM, 3);
    REGW32(MCASP_XINTCTL, 0);
    REGW32_INX_FIELD(MCASP_SRCTL, SRMOD, 4 * (serilizer_no - 0), 0, 0x1);
    REGW32_INX_FIELD(MCASP_SRCTL, DISMOD, 4 * (serilizer_no - 0), 0, 0x3);
    REGW32_INX_FIELD(MCASP_PDIR, AXR, 0, 1 * (serilizer_no - 0), 1);
    REGW32_FIELD(MCASP_PDIR, ACLKX, 1);
    REGW32_FIELD(MCASP_PDIR, ACLKX, 1);
    printf("ACLKX : %x\n",REGR32_FIELD(MCASP_PDIR, ACLKX));
    REGW32_FIELD(MCASP_PDIR, AHCLKX, 1);
    printf("ACLKX : %x\n",REGR32_FIELD(MCASP_PDIR, AHCLKX));
    REGW32_FIELD(MCASP_PDIR, AFSX, 1);
    


    

    REGW32_FIELD(MCASP_GBLCTL, XHCLKRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, XHCLKRST) == 1)
            break;
    }
    REGW32_FIELD(MCASP_GBLCTL, XCLKRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, XCLKRST) == 1)
            break;
    }
        
    REGW32(MCASP_XSTAT,0x0000FFFF);

    REGW32_FIELD(MCASP_GBLCTL, XSRCLR, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, XSRCLR) == 1)
            break;
    }

    /* Write a 0, so that no underrun occurs after releasing the state machine */
    REGW32(MCASP_XBUF + 4 * (serilizer_no - 0),0);
    printf("XBUF : %x\n",(MCASP_XBUF + 4 * (serilizer_no - 0)));

    REGW32_FIELD(MCASP_GBLCTL, XSMRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, XSMRST) == 1)
            break;
    }

    REGW32_FIELD(MCASP_GBLCTL, XFRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, XFRST) == 1)
            break;
    }

    REGW32(MCASP_XBUF + 4 * (serilizer_no - 0),0);
    printf("XBUF : %x\n",(MCASP_XBUF + 4 * (serilizer_no - 0)));

    REGW32_FIELD(MCASP_GBLCTL, XSMRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, XSMRST) == 1)
            break;
    }

    REGW32_FIELD(MCASP_GBLCTL, XFRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, XFRST) == 1)
            break;
    }
    
    if(REGR32_FIELD(MCASP_XSTAT,XCKFAIL) == 1){
        REGW32(MCASP_XCLKCHK,0x00FF0108);
        REGW32_FIELD(MCASP_XSTAT,XCKFAIL,1);
        REGW32(MCASP_XINTCTL,0x00000000);
    }
        
    printf("XCKFAIL : %x\n",REGR32_FIELD(MCASP_XSTAT,XCKFAIL));    

    while(1){


        printf("XCLKCHK : %X\n",REGR32(MCASP_XCLKCHK));

        if(REGR32_FIELD(MCASP_XSTAT,XCKFAIL) == 1){
                REGW32_FIELD(MCASP_XSTAT,XCKFAIL,1);
        }

        for(i = 0; i < 100000; i++);

            if(REGR32_FIELD(MCASP_XCLKCHK,XCNT) > 1)
                break;

            if(REGR32_FIELD(MCASP_XSTAT,XCKFAIL) == 0){
                printf("loop is break here\n");
                    break;
                }
    }
    return Y_SUCCESS;
}




/*!
 * \brief Set hardware properties
play_back: 0 - capture
1 - playback
num_chnls: Number of playback/capture channels
frm_rate: Frame rate
* \param[in] num_chnls
* \param[in] serilizer_no
* \param[in] frm_rate
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */



static int set_hw_params_rx(unsigned int num_chnls,
                unsigned int serilizer_no,
                unsigned int frm_rate,
                struct mcasp_prv_data *pdata)
{
    unsigned int bit_rate;
    unsigned int bit_per_frame = 0;
    unsigned char clk_div;
    struct s_DEVICE_CONFIG *device_config = GET_DEVICE_CONFIG_PTR;
    unsigned long varbit_formats;

    REGW32_FIELD(MCASP_RFMT, RROT, 0);
    REGW32_FIELD(MCASP_RFMT, RBUSEL, 1);

    REGW32_FIELD(MCASP_RFMT, RROT, 0);
    REGW32_FIELD(MCASP_RFMT, RBUSEL, 1);
    REGW32_FIELD(MCASP_RFMT, RRVRS, 1);
    REGW32_FIELD(MCASP_RFMT, RDATDLY, 1);
    clock_settings_rx(pdata);
    GET_BITS(DEVICE_CONFIG_PCM_BIT_FORMATS_BIT_FORMATS_HBIT_POS, DEVICE_CONFIG_PCM_BIT_FORMATS_BIT_FORMATS_LBIT_POS, device_config->PCM_BIT_FORMATS, varbit_formats);
    if (varbit_formats == DEVICE_CONFIG_PCM_BIT_FORMATS_BIT_FORMATS_PCM_FORMAT_S16_LE) {
        REGW32_FIELD(MCASP_RFMT, RSSZ, 7);
        bit_per_frame = 16;
    } else if (varbit_formats == DEVICE_CONFIG_PCM_BIT_FORMATS_BIT_FORMATS_PCM_FORMAT_U8) {
        REGW32_FIELD(MCASP_RFMT, RSSZ, 3);
        bit_per_frame = 8;
    }

    REGW32_FIELD(MCASP_AFSRCTL, FRWID, 1);
    REGW32_FIELD(MCASP_AFSRCTL, RMOD, num_chnls);
    bit_rate = bit_per_frame * frm_rate;
    clk_div = 26000000 / bit_rate;
    REGW32_FIELD(MCASP_ACLKRCTL, CLKRDIV, clk_div - 1);
    REGW32_FIELD(MCASP_AHCLKRCTL, HCLKRDIV, 0);
    REGW32(MCASP_RTDM, 3);
    REGW32(MCASP_RINTCTL, 0);
    REGW32_INX_FIELD(MCASP_SRCTL, SRMOD, 4 * (serilizer_no - 0), 0, 0x2);
    REGW32_INX_FIELD(MCASP_SRCTL, DISMOD, 4 * (serilizer_no - 0), 0, 0x3);
    REGW32(MCASP_PFUNC, 0);
    REGW32_INX_FIELD(MCASP_PDIR, AXR, 0, 1 * (serilizer_no - 0), 0);
    REGW32_FIELD(MCASP_PDIR, ACLKR, 0);
    REGW32_FIELD(MCASP_PDIR, AHCLKR, 0);
    REGW32_FIELD(MCASP_PDIR, AFSR, 0);
    REGW32_FIELD(MCASP_DITCTL, DITEN, 0);
    
    
    REGW32(MCASP_RCLKCHK,0x00FF0008);

    REGW32_FIELD(MCASP_GBLCTL, RHCLKRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, RHCLKRST) == 1)
            break;
    }
    REGW32_FIELD(MCASP_GBLCTL, RCLKRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, RCLKRST) == 1)
            break;
    }
    REGW32(MCASP_RSTAT, 0xffff);
    REGW32_FIELD(MCASP_GBLCTL, RSRCLR, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, RSRCLR) == 1)
            break;
    }


    REGW32(MCASP_RBUF + 4 * (serilizer_no - 0),0);
    printf("RBUF : %x\n",(MCASP_RBUF + 4 * (serilizer_no - 0)));

    REGW32_FIELD(MCASP_GBLCTL, RSMRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, RSMRST) == 1)
            break;
    }
    REGW32_FIELD(MCASP_GBLCTL, RFRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, RFRST) == 1)
            break;
    }

    REGW32(MCASP_XBUF + 4 * (serilizer_no - 0),0);
    printf("XBUF : %x\n",(MCASP_XBUF + 4 * (serilizer_no - 0)));

    REGW32_FIELD(MCASP_GBLCTL, RSMRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, RSMRST) == 1)
            break;
    }
    REGW32_FIELD(MCASP_GBLCTL, RFRST, 1);

    /* Poll */
    while (1) {
        if (REGR32_FIELD(MCASP_GBLCTL, RFRST) == 1)
            break;
    }

    return Y_SUCCESS;
}




/*!
 * \brief Sequence for starting playback. This sequence must contain
any register programming to start clocks
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */

static int start_playback(struct mcasp_prv_data *pdata)
{

    if (REGR32_FIELD(MCASP_AFSXCTL, FSXM) == 1)
        REGW32_FIELD(MCASP_GBLCTL, XFRST, 1);

    if (REGR32_FIELD(MCASP_AFSXCTL, FSXM) == 0)
        REGW32_FIELD(MCASP_GBLCTL, XFRST, 0);

    /* Enable clock */
    REGW32_FIELD(MCASP_GBLCTL, XFRST, 1);
    /*  Toggle the clock */
    REGW32_FIELD(MCASP_ACLKXCTL, CLKXP, REGR32_FIELD(MCASP_ACLKXCTL, CLKXP) ^ 1);
    CALL_TIMER(100);
    /* Disable the transmitter to clear any outstanding XSYNCERR  */
    REGW32_FIELD(MCASP_GBLCTL, XSRCLR, 0);
    printf("XBUF : %x\n",(MCASP_XBUF + 4 * (0 - 0)));
    /*  Toggle the clock */
    REGW32_FIELD(MCASP_ACLKXCTL, CLKXP, REGR32_FIELD(MCASP_ACLKXCTL, CLKXP) ^ 1);
    /* Enable transmitter AFTER CLEARING */
    REGW32_FIELD(MCASP_GBLCTL, XSRCLR, 1);
    printf("XBUF : %x\n",(MCASP_XBUF + 4 * (0 - 0)));

    return Y_SUCCESS;
}




/*!
 * \brief Sequence for starting record. This sequence must contain
any register programming to start clocks
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */

static int start_record(struct mcasp_prv_data *pdata)
{

    if (REGR32_FIELD(MCASP_AFSRCTL, FSRM) == 0)
        REGW32_FIELD(MCASP_GBLCTL, RFRST, 0);

    if (REGR32_FIELD(MCASP_AFSRCTL, FSRM) == 1)
        REGW32_FIELD(MCASP_GBLCTL, RFRST, 1);

    /* Enable clock */
    REGW32_FIELD(MCASP_GBLCTL, RFRST, 1);
    /*  Toggle the clock */
    REGW32_FIELD(MCASP_ACLKRCTL, CLKRP, REGR32_FIELD(MCASP_ACLKRCTL, CLKRP) ^ 1);
    CALL_TIMER(100);
    /* Disable the transmitter to clear any outstanding XSYNCERR  */
    REGW32_FIELD(MCASP_GBLCTL, RSRCLR, 0);
    /*  Toggle the clock */
    REGW32_FIELD(MCASP_ACLKRCTL, CLKRP, REGR32_FIELD(MCASP_ACLKRCTL, CLKRP) ^ 1);
    /* Enable Receire AFTER CLEARING */
    REGW32_FIELD(MCASP_GBLCTL, RSRCLR, 1);

    return Y_SUCCESS;
}




/*!
 * \brief Sequence for stopping playback. This sequence must contain
any register programming to stop clocks
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */

static int stop_playback(struct mcasp_prv_data *pdata)
{

    REGW32_FIELD(MCASP_GBLCTL, XFRST, 0);
    /*  Toggle the clock */
    REGW32_FIELD(MCASP_ACLKXCTL, CLKXP, REGR32_FIELD(MCASP_ACLKXCTL, CLKXP) ^ 1);

    return Y_SUCCESS;
}




/*!
 * \brief Sequence for stopping record. This sequence must contain
any register programming to stop clocks
 * \return Success or Failure
 * \retval  0 Success
 * \retval -1 Failure
 */

static int stop_record(struct mcasp_prv_data *pdata)
{

    REGW32_FIELD(MCASP_GBLCTL, RFRST, 0);
    /*  Toggle the clock */
    REGW32_FIELD(MCASP_ACLKRCTL, CLKRP, REGR32_FIELD(MCASP_ACLKRCTL, CLKRP) ^ 1);

    return Y_SUCCESS;
}

Application :

    //mcasp_init initilize or start the mcasp
    if((ret = mcasp_init(pdata,NULL)) != 0){
        printf("fail to initlization\n");
        return -1;
    }
    printf("ret valu of init : %u\n",ret);
    
    //this api set the device configuration mean in which format data has to transfer
    set_DEVICE_CONFIG_TRANSFER_MODE (I2S_MODE,pdata);
    switch(get_DEVICE_CONFIG_TRANSFER_MODE (pdata)){    
        case 0 : printf("I2S\n");
            break;
        default : printf("not set\n");
            break;
    }

    //this api set the device configuration set pcm bit format
     set_DEVICE_CONFIG_PCM_BIT_FORMATS ( PCM_FORMAT_S16_LE ,pdata);
     switch(get_DEVICE_CONFIG_PCM_BIT_FORMATS (pdata)){
        case  PCM_FORMAT_S16_LE : printf("pcm_sign_16_le\n");
            break;
        default : printf("not set\n");
            break;
    }

    //this api is used to set the clock is master or slave
    set_DEVICE_CONFIG_CLOCK_MASTER_SLAVE (MASTER ,pdata);
    switch(get_DEVICE_CONFIG_CLOCK_MASTER_SLAVE (pdata)){
        case  MASTER : printf("MASTER\n");
            break;
        default : printf("not set\n");
            break;
    }

    //this api is used to set the polarity
    set_DEVICE_CONFIG_CLOCK_POL (0,pdata);
    printf("clock polarity %d\n", get_DEVICE_CONFIG_CLOCK_POL (pdata));

    //this api is used to set clock caps
    set_DEVICE_CONFIG_CLOCK_CAPS (0,pdata);
    printf("caps : %d\n",get_DEVICE_CONFIG_CLOCK_CAPS (pdata));

    //this api set Mcaspto in loop back mode
    if((ret = apis->loopback(pdata)) < 0){
        printf("fail to set loop back \n");
        return -1;
    }

    num_chnls = 2;
    serilizer_no = 0;
    frame_rate = 96000;
    //this api set transmitter parametter
    if((ret = apis->set_hw_params_tx(num_chnls, serilizer_no, frame_rate ,pdata)) != 0) {
        printf("fail set_hw_params_tx\n");
        return -1;
    }
    printf("after hw_params_tx\n");

    //api start play back
    if((ret = apis->start_playback(pdata)) != 0) {
        printf("fail star_playback\n");
        return -1;
    }

    serilizer_no = 0;
    sample_sz    = 16;
    //api write data in mcasp
    if((ret = apis->device_write(bird,num_chnls, serilizer_no,sample_sz,pdata)) != 0) {
        printf("fail device_write\n");
        return -1;
    }
    printf("before start_record and after write\n ");


    num_chnls = 2;
    serilizer_no = 1;
    frame_rate = 96000;

    //this api set transmitter parametter
    if((ret = apis->set_hw_params_rx(num_chnls, serilizer_no, frame_rate,pdata)) != 0) {
        printf("fail set_hw_param_rx\n");
        return -1;
    }
    printf("after the set_hw_params_rx\n");
    


    

    //this api start record
    if((ret = apis->start_record(pdata)) != 0) {
        printf("fail star_record\n");
        return -1;
    }
    printf("before device read and after start_record\n ");

    serilizer_no = 1;
    sample_sz    = 16;
    //this api read data
    if((ret = apis->device_read(buff,num_chnls,serilizer_no,sample_sz,pdata)) != 0) {
        printf("fail device_write\n");
        return -1;
    }
    printf("after device read\n ");
    
    printf("buff[0] : %c\n",buff[0]);
    printf("buff[1] : %c\n",buff[1]);
    
    //this api stop playback
    if((ret = apis->stop_playback(pdata)) != 0) {
        printf("fail star_record\n");
        return -1;
    }

    //this api stop record
    if((ret = apis->stop_record(pdata)) != 0) {
        printf("fail star_record\n");
        return -1;
    }
    mcasp_yexit(pdata);