We are using the TMS320C6472 6-core DSP and will be loading code using the HPI Interface. It appears that some of the documentation for using this interface for the C6472 conflicts each other.
The Bootloader User’s Guide (SPRUEC6D), under the C6472 HPI Boot section (4.3.1), states “The No boot and HPI boot are the same as the C6454/55 processes described in Section 2.3.1 for No boot and Section 2.3.2 for HPI boot.”. Section 2.3.2 describes the HPI Boot process for the C6454, which only contains a single core. It explains that the user should load code into the base of the L2 memory and then generate an HPI interrupt to begin code execution.
The C6472 datasheet describes a somewhat different HPI boot process. It explains the user should load code (to shared or local L2 memory) and then write a 1 to the BOOT_COMPLETE register to bring the cores out of reset. It also states that you may configure the BOOT_ADDR register to select the beginning execution address for each core.
Can someone please clarify the proper HPI boot process for the C6472?
