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SRAM, NOR and NAND Interface with 66AK2H14

vijetha hn
Expert 1230 points
Other Parts Discussed in Thread: 66AK2H14

Hi,

We have requiremnent of following memory interfaces to 66AK2H14 device. Currently we are in design planning stage. Please help us how to plan these interfaces with 66AK2H14.

1. NOR Interface

2. DDR3 

3. SRAM Interface.

4. NAND Interface

 

We will connect NOR flash to SPI1 interface of 66AK2H14 and 2 nos of 16 bit DDR3 devices to 72-Bit DDR3 EMIF interfaces of 66AK2H14.

 

How can we connect SRAM and NAND devices to 66AK2H14 ?

The memory interfaces left in 66AK2H14 is EMIF16. Please specify is there any option of connecting 2 independent SRAM and NAND interfaces to 66AK2H14 through EMIF16 or any other interfaces.

Regards,

Vijetha

 

  • 0
    TI__Guru 65405 points
    Hi Vijetha,

    I've forwarded this to the HW design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Mastermind 46460 points

    Vijetha,

    The 66AK2H14 natively connects to asynchronous memories over the AEMIF.  This includes parallel NOR, NAND and SRAM.  NOR can also be supported over SPI.  Please review to the EVM design at http://www.ti.com/tool/evmk2h which links to http://www2.advantech.com/Support/TI-EVM/EVMK2HX.aspx for the detailed design files.  The EVM contains NAND FLASH on the AEMIF and NOR FLASH on SPI.  It also shows implementation of DDR3 SDRAM either as a flattened implementation or use of a UDIMM.  If you are only using a single DDR EMIF, you should use the first since it supports a larger addressable space.

    Tom

  • 0 in reply to Tom Johnson 16214
    Expert 1230 points

    Hi

    Thank you for the response.

    I did not get the point clear.

    I understood your points in following way :

    1. Use NOR FLASH device with SPI Interface of Processor - Clear, I will implement in that way.

    2. Use NAND FLASH with AEMIF interface - Clear I will use a SLC NAND FLASH of 16 bit data width with EMEIF16 of the processor

    3. Use DDR3 with DDR3 EMEIF - Clear, I have requirement of 2 nos of DDR3 in parallel, hence I will connect 2 nos of 2GB devices with 2 DDR3 EMIFs of the processor.

    Now remaining requirement is SRAM. Where I will connect SRAM with this plan ? Whats your suggestion on connecting SRAM with processor in presence of above interfaces connections.

    If connecting SRAM is not all possible, then can I connect NOR on SPI1, Serial NAND on SPI2 and ASRAM on AEMIF interfaces? This was my alternate plan. If you have better plan please suggest. 

    Regards,

    Vijetha

  • 0 in reply to vijetha hn
    TI__Mastermind 46460 points

    Vijetha,

    The AEMIF is an Asynchronous External Memory InterFace.  This AEMIF has multiple chip selects.  It can support multiple asynchronous memory devices.  Therefore, you can connect both parallel NAND FLASH as well as parallel SRAM to it - each will have a separate chip select.  For more information, refer to the KeyStone Architecture External Memory Interface (EMIF16) User Guide (SPRUGZ3A) at .

    Tom