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C6748 DDR2 connection

AD53214
Prodigy 45 points

Other Parts Discussed in Thread: TMS320C6748

I have mistake on PCB design with TMS320C6748.

DDR2 memory has been connected to DSP DDR2 interface with the swapped data bus.

DSP DDR_D<0> connected to DDR2 memory D<15> and so on.

Because of it DQS0 and DQM0 lines currently control byte 1 D<15..8> and DQS1, DQM1 control byte 0 D<7..0>. Address bus is connected properly.

How this can effect DSP communication with DDR2 memory?

Is there any chance that this communication can work?

DDR2 interface will be configured to 16 bit access

  • 0
    TI__Mastermind 43875 points

    AD,

    DQS/M0 must always go with D<7..0> and DQS/M1 must always go with D<15..8>

    If not, then the timing controls will be affecting the wrong data bytes.

    Additionally, this will likely stop any byte wise operations from working at all if it is incorrect.

    This arrangement may potentially work initially but will likely have stability issues over temperature/time.

    BR,

    Steve

  • 0
    Prodigy 45 points

    Thank you Steve for quick answer and I if possible I have three questions below:

    1.       In this case when the data bus is swapped I understand that the timing will be affected, would be possible to gain more timing margin if I decreasing the DDR clock for instants from 150MHz to 50MHz?

    2.        If DDR2 interface is configured for 16bit access then is there any change that 8bit access can happen to DDR chip for  example from the DSP Bios ?

    3.       For correct 16 bit access when there is no mistakes on the bus  DDR controller will clock D< 7..0> with DQS0 and D<15..8> with DQS1, how far apart is the edge of the DQS0 from  DQS1 during this 16 bit access.

     

     

     

     

  • 0 in reply to AD53214
    TI__Mastermind 43875 points

    AD,

    To be honest I am reaching the limits of my knowledge now but will try my best...

    1) Slowing down should give more margin I believe, yes.

    2) It can, but I am not sure how likely. There are certainly byte wise instructions in the ARM/DSP instruction set, but I don't really know how much they are used.

    3) Your best bet is to look at some JEDEC specifications for these timings and the datasheets for both the processor and the memory.

    Sorry I am not more help here.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 45 points

    Thank you very much; I know that some of my questions are difficult to get the answer.