Hello
Is it possible to control output phase of I2C SCL?
In my board, there's too tight margin between I2C master and slave.
I have found there is a register for control of duty rate of clock.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hello
Is it possible to control output phase of I2C SCL?
In my board, there's too tight margin between I2C master and slave.
I have found there is a register for control of duty rate of clock.