Something wrong with cache and DMA

Yuanchi Yu

I'm running a data copy program on DM6467 EVM and
having some trouble with cache and DMA.

The data section is from DDR to DDR, like from 0x88000000 to 0x88018700.
When I do not enable caching, DMA works fine.
Once caching enabled, DMA copies nothing from src to dst,
but it's OK with memcpy().

So how can I enable cache and DMA function at the same time ?
Thanks a lot.

over 15 years ago

0 Andrew Muehlfeld over 14 years ago

Intellectual 720 points

I'm just learning about DMA on DaVinci processors, and am not an expert. DMA does transfers directly with physical memory, ignoring any data that might have been modified in a cache. In order to to use DMA on cached memory, you need to do a Write Back, or a Write Back Invalidate, immediately prior to beginning the DMA transfer.

Here are some potentially useful functions.

Memory_cacheWb()

Memory_cacheWbInv()

Memory_cacheInv()

0 Chris Ring over 14 years ago in reply to Andrew Muehlfeld

TI__Genius 17205 points

This article may also help:

http://processors.wiki.ti.com/index.php/Cache_Management

Note that the Memory_* APIs Andrew mentions are a part of Codec Engine (ti/sdo/ce/osal/Memory.h). If you're not using Codec Engine, you will find similar cache management APIs in BIOS (BCACHE_* for BIOS 5, and Cache_* for BIOS 6).

Chris

Processors

Processors forum

Something wrong with cache and DMA