AM335x layout with 2xDDR3

Alpesh Borad

Other Parts Discussed in Thread: AM3352

Hi,

We are using AM3352 Processor with DDR3 Memory(2nos)..

We are following the 6 layer Stack up as below.

L1	TOP
L2	GND
L3	SIG
L4	SIG
L5	GND\VCC
L6	SIG

When we route the DDR3 signal in L4 and L6 in that case it gets the reference of L5 and when route in L1 and L3 in that case it get reference of L2.

In L5 +1.5V plane is created which covered the DDR3 area so the the routing in L4 and L6 of DDR3 traces get reference of +1.5V and route of L1 and L4 get reference of GND.

So Is it OK to route DDR3 signals with different reference of +1.5V and GND?

Is there affected on RE and Functionality?

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

It should be OK, as long as the reference plane is unbroken.

0 Alpesh Borad over 8 years ago in reply to Biser Gatchev-XID

Intellectual 990 points

Thanks for the Reply,

I have also confusion.

If I have route the DDR_A0 signal in TOP layer so it get reference of L2(GND) and then I take via in DDR_A0 signal and route in BOTTOM which get reference of L5(VCC +1.5V).

So here DDR_A0 signal get two references , When it in TOP it get GND reference and half routing is in BOTTOM it get +1.5V reference.

Same signal it half route in TOP and half Route in BOTTOM in that case it gets two different reference so Is it OK to route ot it will create ant performance\RE issue?

Regards,
Alpesh Borad

0 Biser Gatchev-XID over 8 years ago in reply to Alpesh Borad

TI__Guru**** 393215 points

It's best to keep the a single signal routed along the same reference plane. The same is valid for the signal groups - Address/Control, DQ0 and DQ1 signals should be routed along a common reference for each group. You should perform SI analysis if you are unsure in the layout.

0 Alpesh Borad over 8 years ago in reply to Biser Gatchev-XID

Intellectual 990 points

Thanks for the Guidance,

Actually we have no facility to check SI so Is it advisable to route ( Same Net ) half trace in TOP with GND reference and half trace in BOTTOM with +1.5V Reference?

Beast Regards,
Alpesh

0 Biser Gatchev-XID over 8 years ago in reply to Alpesh Borad

TI__Guru**** 393215 points

See processors.wiki.ti.com/.../DDR_Routing_Checklist

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AM335x layout with 2xDDR3