Customer found a real issue about the PTP.
To summarize the problem: the PTP will have really poor precision…
To explain:
- The Timestamping subsystem can only be clocked by the Core PLL
- The core PLL is also used for a large number of peripherals (Interface and/or Functional): DDR, Display, Ethernet …
But this PLL is not tunable and using an external clock as source for this PLL is probably not a good idea considering other peripherals. - That limitation implies that the PTP time can only be corrected by offset and NOT by drift correction! I suspect really poor results due to drift between two offset corrections and software conversion from HW timestamps to PTP time (in ns)
I don’t find a lot on the subject but some posts on the TI forum seem to confirm that:
https://e2e.ti.com/support/arm/sitara_arm/f/791/t/187485
Can you please let me know if AM335x MPUs are tailored for PTP applications and how to configure the MCU properly for and accurate PTP timestamping?
Regards, Bernd
