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AM572x PCIe how to restrict EP from access to RC memory space

Denny%20Yang99373
Expert 3805 points
Other Parts Discussed in Thread: AM5728

Hi all,

We use AM5728 PCIE as RC and a FPGA work as EP.

Work as default, EP can access all RC's DDR memory space. Now we have a questions: how to restrict the EP's access space?

Setup BAR0/1 or MMU2?

I have found there is a MMU2 for PCIE, how to use MMU2? Do we have any example about MMU2?

thanks!

BR,
Denny

  • 0
    TI__Guru**** 393215 points
    Hi,

    What software are you using?
  • 0 in reply to Biser Gatchev-XID
    TI__Expert 3805 points

    We run processor sdk linux version. thanks!

  • 0 in reply to Denny%20Yang99373
    TI__Guru**** 393215 points
    Thanks. The software team have been notified. They will respond here, but there may be a delay due to holidays in the USA.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points

    Denny,

    When AM572x and FPGA connected via PCIE, their PCIE data space is "connected/mapped". For example, on AM572x side, this data space is 0x2000_0000 region, if we enabled outbound translation, then any R/W into 0x2000_0000 data address will be translated into another address goes into FPGA side. The FPGA has PCIE BARs to match/reject the incominmg address and maybe inbound translation to convert it into FPGA internal memory space.

    In your case, FPGA intiates the PCIE read/write from/to AM572x, in the AM572x side if you don't configure the BAR to accept the incoming address, the EP is not able to access the RC. Or you configured the BAR, but no configuration of inbound translation, the access goes directly into the incoming address, which may be not available in AM572x memory. In this case, EP is not able to access the RC as well.

    When the RC side runs on ARM15, in our Processor SDK RTOS example we have MMU setup to map the virtual address to physical address in .cfg file. If no such setup, the EP is also unable to access RC.

    For the Linux, I am not familiar with how they setup: MMU, BAR and inbound translation on AM572x, I routed your thread to our Linux team.

    Regards, Eric

  • 0 in reply to lding
    TI__Expert 3805 points

    Hi Eric,

    Thanks for your update!

    I want the demo A15 work as RC and FPGA work as EP. The RC have made the memory restriction when EP access. 

    Does the processor sdk rtos version have this demo?

    If yes, which address range it can been accessed by EP? And please send me the detailed file path which I can refer.

    thanks!

    BR,

    Denny 

  • 0 in reply to Denny%20Yang99373
    TI__Guru* 95265 points

    Denny,

    The Processor SDK RTOS PCIE example shows how the two TI AM57X EVM exchanging data with PCIE. We don't do the restriction of EP accessing RC memory.

    Based on my previous explanation, the data exchange needs: MMU setup, BAR configuration, outbound translation and inbound translation. If you break/unconfigure any of them, then EP can't access RC memory.

    Please check pdk_am57xx_1_0_4\packages\ti\drv\pcie\example\sample\am572x\armv7\bios\pcie_sample_wSoCFile.cfg for MMU setup; pdk_am57xx_1_0_4\packages\ti\drv\pcie\example\sample\src\pcie_sample.c for BAR, OB, IB translation setup.

    Regards, Eric