About the code memory

Have you adjusted the L1P cache settings before loading the program? This will have to be done after any GEL_Reset() also.

Other than for very special cases when you are absolutely certain this is the best way to implement your application, I would recommend using L1P as 100% cache and load your code into L2SRAM. There are cases where it is a big benefit to move some code to L1P SRAM, but those are pretty rare.

Regards,
RandyP

OK。 in my cmd file there are：

#ifdef DSP_CORE
/****************************************************************************/
/* */
/* DSP 专有内存区域 */
/* */
/****************************************************************************/
DSPL2ROM o = 0x00700000 l = 0x00100000 /* 1MB L2 DSP 本地 ROM (DSP ROM Bootloader) */
DSPL2RAM o = 0x00800000 l = 0x00040000 /* 256kB L2 DSP 本地 RAM */
DSPL1PRAM o = 0x00E00000 l = 0x00008000 /* 32kB L1 DSP 本地程序 RAM */
DSPL1DRAM o = 0x00F00000 l = 0x00008000 /* 32kB L1 DSP 本地数据 RAM */
#endif

/****************************************************************************/
/* */
/* 公共内存区域 */
/* */
/****************************************************************************/
SHDSPL2ROM o = 0x11700000 l = 0x00100000 /* 1MB L2 共享内置 ROM */
SHDSPL2RAM o = 0x11800000 l = 0x00040000 /* 256KB L2 共享内置 RAM */
SHDSPL1PRAM o = 0x11E00000 l = 0x00008000 /* 32KB L1 共享内置程序 RAM */
SHDSPL1DRAM o = 0x11F00000 l = 0x00008000 /* 32KB L1 共享内置数据 RAM */

about the dsp internal memory . I use the SHDSPL1PRAM, what the different wit the DSPL1PRAM in above? are they the same memory?

Do not use the L1P and L1D memories for program or data storage unless you have studied in detail how they operate and how to use and manage them. Since you have not stated a device, I cannot point you to the documentation, but there is generally a Technical Reference Manual or a Two-Level Memory document or a DSP System document that contains information on the caches. You can also go to our training website to find material relevant to your specific device or something similar.

The xxxL1PRAM and xxxL1DRAM lines in the linker command file are there for completeness but should rarely be used. By default, all of our recent DSP cores come out of reset with L1P and L1D in 100% cache mode, so 0kB of SRAM is available for use. This is most likely the reason for your problems.

You should change to a different memory location for your program and let the cache work the way it is supposed to work, speeding up your repeated accesses to slower memories. Since the program loaded into the L1P space is getting trashed, you are also using other memory regions that count on the cache to exist, and accesses to those are overwriting your code loaded directly into the L1P memory. If you turn off L1P caching, those other programs will run much slower, so stay with 100% L1P cache and use another memory location.

Yes, SHDSPL1PRAM and DSPL1PRAM are the same physical memory. The DSP core can access locations by using either address, but external bus masters (external to the DSP core, not just to the device) must use the SHDSPxxxx address range.

Regards,
RandyP

Please look in the documents so you understand how it works. Since you are going against my recommendation to avoid switching the L1 caches, the best place to look to understand the changes is in the GEL files. Search for 'cache' and find where it sets or changes cache settings. You can compare that with what you read about in the documents to help you understand how it works and how to set it.

Regards,
RandyP