K2 Hyperlink layout rules

Hi Andy,

I've forwarded this to the hyperlink experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

Any free feedback on this question? Thank u very much.

Andy,

What is the current length of the HyperLink differential pairs on the customer board ?

Regards,
Senthil

Hi Andy,

The HyperLink is a challenging interface to route and operate. The routing guidelines must be followed closely if your expecting to operate the interface at high speeds. Although signals will travel at different speeds through different materials, the difference in length would be in thousands of inches and not in inches. Let me ask a couple of questions. 

1) HyperLink requires all four lanes to be routed. Have you routed all four lanes?

2) What speed are you attempting to operate the interface? Does it operate at lower speeds?

3) With the exception of the length requirement, have you followed all the other routing guidelines concerning impedance, reference planes, and the number of vias?

Regards,

Bill

Bill, 

First let me answer your questions directly.

1) Yes, all four lanes are routed.

2) Operate as least 10Gbps. The current issue is that it cannot work if both two hyperlinks are enable, but it can work stably with only one hyperlink enabled.

3) Customer can understand all the other requirements and can satisfy all, but only cannot understand the length requirement mentioned above.

For your comments I cannot understand the "the difference in length would be in thousands of inches and not in inches", does this mean the difference in length should be millesimal? 

And for the current issue mentioned in about 2), do u have any comments on why it cannot work with two hyperlinks enabled, but can work with each enabled separately?

Thank u very much for your reply.

BR,

Andy

Hi Andy,

There is some new information in your last post. First let me comment on your length question. The reason for limiting the length is not associated with propagation delay.  The reason for limiting the length of the traces is to limit signal loss across the run. HyperLink is a very high speed interface designed to operate between two devices on the same PCB. It was determined that the drivers for the interface should be able to driver four inches of trace based on the loss profile for standard materials across temperature and process.  This is described in advisory 31 in the errata document. 

In the post above you reported that the customer has routed both HyperLink interfaces with four lanes connected for each interface. You also specified that each interface is working correctly if enabled individually but you see errors if both are active. It may be possible that there is some cross talk between the two interfaces if the traces are routed in the same proximity. If the interfaces are routed for a length greater then four inches, the loss on the line may be enough to allow for greater crosstalk between signals on the board. It's also possible that this could be a software or throughput issue within the K2K. 

Can you provide details on the failure observed? Do errors only occur when data is being passed on both interfaces? If one interface is actively passing data and the other interface is enabled but not passing data, do you see errors? 

Are the two interfaces routed close to each other? Are there any parallel runs for the traces of each interface?

Regards,

Bill

Hello
TCI6638K2K has two Hyperlink interfaces.
The Advantech EVM can be checked for the layout utilized.
In the MCSDK Serdes projects, using the TCI6638K2K EVM, and Advantech RTM Loopback card, a loopback connection can be tested from Hyperlink0 to Hyperlink1.
advantech.com/www/support/TI-EVM/download/Schematics/PDF/K2H_K2EVM-HK_SCH_A104_Rev3_0.pdf
There are sample layout files for the EVM also.

In advisory 31, www.ti.com/.../sprz401e.pdf, pg42, the customer needs to characterize the serdes channel on the customer board from the Tx output through to the series cap to Rx input for each differential pair. As Bill asked, you have the 4 differential pairs and sideband signals.

Having your customer block diagram would help
Here is a simplified one
K2KA Hyperlink0 <-> K2KB Hyperlink0
K2KA Hyperlink1 <-> K2KB Hyperlink1

So in the characterization of these links, you would have used the Serdes BER tests, and make a custom transmit and receive section (making sure that both devices use the same source clock). You would adjust using the BER and PRBS test in the MCSDK serdes project, and the Serdes User Guide, and the Hyperlink User Guide, each of the 8 lane sets between the two devices.

You would then in your software tests, make sure you use the selected Tx drive strength, Tx DFE Cm,C1,C2
and allow each of the Rx serdes to adapt. If the customer has followed the Hardware Design Guide, and Serdes User Guide for Hyperlink, you should have a low error rate channel ideally at 10GLine rate.

As Bill indicated if the two Hyperlink interfaces interfere with each other, when you test them one at a time, the interference source from the other link is not present.

Advisory 31 - you should have less Insertion loss than whats in the graph.
www.ti.com/.../sprz401e.pdf

Hardware Design Guide for Keystone II devices - this has several layout constraints, the 4" constraint is listed in section 8.2

You might review these layout 8.2 sections with the customer. If the customer has an unpopulated board, they could make the VNA measurements in the Advisory 31 also.

Regards,
Joe Quintal

Hi Bill,

Sorry for the late reply. My customer's current PCB material Er=3.7, the insertion loss = 0.66db/Inch@6.144G, the maximum length is about 9inch, could u pls help evaluate the possible maximum driver capability, and can u help give the maximum length requirement based on customer's pcb material?

And for the standard material mentioned in your post, could u pls help give the related PCB Er value?

Really great appreciation for your valuable reply and pls continue to support it, thanks again.
Andy