Unused PCIe pins on C6657

Omin Chou

Hi all,

I did not want to use PCIe Receive Data pins as shown below. How did I handle them? Add external resistors to ground? Thanks in advance.

B.R.

over 8 years ago

0 Raja over 8 years ago

TI__Guru* 81335 points

Hi,

Please refer the keystone schematic checklist below,

processors.wiki.ti.com/.../Keystone_Multicore_Device_Family_Schematic_Checklist

Thank you.

0 Omin Chou over 8 years ago in reply to Raja

Genius 3555 points

Hi Raja,

Thanks for your reply.
But the schematic checklist does not mention how to handle unused PCIe Rx input pins instead of PCIe interface is not required.
Because I still need PCIe Tx signal to do other work.

Thanks in advance.

B.R.
OC

0 Senthilkumar Srinivasan over 8 years ago in reply to Omin Chou

TI__Mastermind 43660 points

OC,

For what purpose you are going to use PCIe TX pins ? From my understanding, you cannot leave the RX pins unconnected when you use TX pins.

Regards,
Senthil

0 Omin Chou over 7 years ago in reply to Senthilkumar Srinivasan

Genius 3555 points

Hi Senthil,

Sorry for my wrong message.
I only used 1 lane and lane 2 would not be used. How did I handle PCIERXN1 (AD10) and PCIERXP1 (AD11) input pins?
Thanks a lot.

B.R.
OC

0 Senthilkumar Srinivasan over 7 years ago in reply to Omin Chou

TI__Mastermind 43660 points

OC,

All unused PCIe lanes must be left floating and the unused lanes should be properly configured in the MMR.

Please refer section 6.6.3 for unused PCIe pin requirement in below link.

www.ti.com/.../sprabi2c.pdf

Regards,
Senthil

0 Omin Chou over 7 years ago in reply to Senthilkumar Srinivasan

Genius 3555 points

Hi Senthil,

It's very clear to me. Thanks so much.

B.R.
OC

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Unused PCIe pins on C6657