TMS320VC5502 PLL initialization problem.

Hello,

The DSP input clock are 20MHz. I'm trying to init PLL but the LOCK bit in PLL control/status register never becomes 1.

Did anybody had the same problem? 

#define     PLLCSR      (*(volatile ioport unsigned short int *) 0x00001C80)
#define     CK3SEL      (*(volatile ioport unsigned short int *) 0x00001C82)
#define     PLLM        (*(volatile ioport unsigned short int *) 0x00001C88)
#define     PLLDIV0     (*(volatile ioport unsigned short int *) 0x00001C8A)
#define     PLLDIV1     (*(volatile ioport unsigned short int *) 0x00001C8C)
#define     PLLDIV2     (*(volatile ioport unsigned short int *) 0x00001C8E)
#define     PLLDIV3     (*(volatile ioport unsigned short int *) 0x00001C90)

void PLLSetup( void )
{
    volatile unsigned long cnt = 0;

    // 1. Switch to bypass mode by setting the PLLEN bit to 0.
    PLLCSR &= ~BIT0;
    for( cnt = 0; cnt < PLL_SETUP_WAIT; cnt++ )
        asm("  nop");

    // 2. Set thePLL to its reset state by setting the PLLRST bit to 1.
    PLLCSR |= BIT3;
    // 3. Change the PLL setting through the PLLM and PLLDIV0 bits.
    PLLM    = 5; // 0x0F;
    PLLDIV0 = ( unsigned short )( BIT15 | 0x01 );

    // 4. Wait for 1 µs.
    for( cnt = 0; cnt < PLL_SETUP_WAIT; cnt++ )
        asm("  nop");
    // 5. Release the PLL from its reset state by setting PLLRST to 0.
    PLLCSR &= ~BIT3;

    // 6. Wait for thePLL to relock by polling the LOCK bit
    while(( PLLCSR & BIT5 ) == 0) 
        asm("  nop");
    // 7. Switch back to PLLmode by setting the PLLEN bit to 1.
    PLLCSR |= BIT0;

}

Thanks in advance.

Kirill