Unable to Configure PLL1 Controller from DSP

Hi Mitesh,

I've forwarded this to the experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

Mitesh,

The bootloader provided in the Starterware is already configuring the PLL0 and PLL1 to 300 Mhz as done in the GEL file and it also enables all the PSC corresponding to all modules used in the bootloader. Can you please specify what you have changed and attach your code here so that we can provide inputs. also please describe youe debug setup, did you modify the bootloader and then create boot image and load the image to NAND and then test the boot? Why do you suspect that this is a PLL And PSC initialization issue. From your description it appears that the application is booting from the flash and hangs in the HWI ISR which is not setup by the boot code but your application.

When you tested your changes did you remove the default GEL loaded in CCS. When testing bootloader, you should remove all other GEL files as the Bootloader code will perform all the initialization. one way to compare the GEL and the bootloader settings is to run the GEL and save the PSC, PLL register values and then compare then to the values of the same registers when booting the application using the bootloader.

Regards,
Rahul

Hi Rahul, thanks a lot for your reply. Yes, you are right the bootloader does set the PLL and PSC but I want to change the clock to 475MHz. Yes, I could change it in the bootloader provided in the StarterWare but I wanted to do it in the DSP application so just to see it does what I think it should. 

So to test that, I use the GEL file to wake DSP up and it also sets the PLL and PSC but then in my main function, I change the clock PLL0 which seems to at least complete the  steps but when it reaches PLL1 to change the DDR2 clock it seems to not complete it. I have changed the configuration steps so that it doesn't clear the power down flag but still no change. I will try to change the PLL to 475MHz in bootloader and get back to you.

One more thing, my DSP application is loading the code into DDR2 (I have changed this in the *CMD file) and if I want to use the JTAG for debug, I will have to use the CCS debug option to run the application, right? there is no-way I can use the JTAG when booting the design from NAND Flash. But when I load this with the GEL file on my prototype hardware the GEL file fails to write in some PLL config register. But seems to work on the OMAPL138 LCDK board, I don't understand why? Could you suggest on this please. Not sure if it has to do anything with the user mode. Thanks

Regards,

Mitesh

Mitesh,

Which clock are you trying to set to 475Mhz. The max speed(SYSCLK1) on OMAP-L138 is 456 Mhz. Please use the following spreedsheet to simulate your clock setup:

processors.wiki.ti.com/.../AM18xx

when you boot from NAND flash you can remove the GEL from the target configuration before you connect to the DSP, this way only the bootloader performs the PLL, PSC and DDR and not the GEL file. but when you are just trying to test your application independent of the bootloader, you will need the GEL to setup the clocks and PSC and DDR.  

Regards,

Rahul

Hi Rahul, sorry I meant, 456MHz for the DSP.
So there is not way to use DSP without the GEL file to load application from CCS?

Hi Rahul, yup got it;)

If I have an application loading the design on the DDR2. So I definitely need to use the GEL file when I load the application from the CCS. 

The problem I have is when I do this on my prototype HW with OMAPL138 its giving me writing to some PLL register error. 

What changes would you expect to be done in the GEL file when the target board is not OMAPL138 LCDK? Thanks

Regards,

Mitesh

What is the error that you see with PLL1. HAve you checked that the all your clocks are within the spec and you are following the PLL initialization sequence. Good way for you to start would be to compare your changes to the LCDK GEL or provide the updated GEL here to see if we can identify any issue with it.

Also, here are some hardware configuration and debugging tricks while configuring DDR on this device:
processors.wiki.ti.com/.../OMAP-L138_Hardware_Design_Guide

Regards,
Rahul

Hi there, right not sure why but GEL file seems to work now. One thing, I notice, do you expect users to use the boot in EMU Debug boot when using JTAG to download the application to the chip?

And the variant "OMAPL138" in the RTSC selection is right? or should I still be using "LCDKOMAPL138"?

The reason I ask is, I have noticed when I create a buffer using "Memory_alloc" its allocates the buffer in the internal DSP RAM when "OMAPL138"  is set but I want to use DDR2. Thanks.