Is Cache coherency is supported in C55x? and what are the APIs for Cache coherency in c55x?
Is there Functionalities for operations like Write-back, Invalidate, Invalidate-Writeback???(Any Hardware support)
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Is Cache coherency is supported in C55x? and what are the APIs for Cache coherency in c55x?
Is there Functionalities for operations like Write-back, Invalidate, Invalidate-Writeback???(Any Hardware support)
Hi Akshay,
Which device are you looking at?
I can't think of any C55x device that has a cache - usually just single access RAM (SARAM) and dual access RAM (DARAM) for internal memory and EMIF for external SDRAM.
You can make a software cache with the internal RAM and manage it how you like.
Regards,
Mark
Hi Akshay,
The TMS320VC5510 does have an instruction cache that is used when executing a program from external memory. There is 320kB of on-chip memory, which means most programs can reside in internal memory alone. But when the EMIF is used, the 2-way set associative instruction cache and two additional RAM sets can be used to minimize external memory accesses, which reduces instruction fetch time and system power. RAM sets can hold up to 4K bytes for frequently used functions.
Cache coherence is required when multiple processors access the same external memory, and make changes that would be missed if another processor accesses the stale version of that data in its cache (instead of accessing the external memory). This is most important for data caches since changes to program code during the execution is not likely (ie. self-modifying code). C5510 does not support cache coherence in that regard. However, the cache does have some neat features to flush and freeze (no updates for a cache miss).
For more information, refer to SPRU576D - TMS320VC5510 DSP Instruction Cache Reference Guide - http://www.ti.com/lit/ug/spru576d/spru576d.pdf
And SPRU312 - TMS320C55x DSP Functional Overview http://www.ti.com/lit/ug/spru312/spru312.pdf
Hope this helps,
Mark