Hi,
I am using Keystone II (K2H, K2K, K2L). Processor speed is 1.2GHz, so EMIF clock period is 5nS.
I have connected a NAND flash to the EMIF, and I am calculating the EMIF timing parameters. (Setup, strobe, hold etc)
I can meet all the timing parameters for isolated read and write cycles, but I cannot achieve the appropriate delay from a read to a write or a write to a read.
For example, the NAND requires a 100nS delay from the end of a read to the beginning of a write (Trhw). This corresponds to 20 EMIF clock cycles. The TA field only allows up to 4 cycles for turnaround.
Another issue is that the DSP will start driving the data bus to a parked value when the EMIF is idle. After a FLASH read, the FLASH data bus is not tri-stated for up to 65nS. The DSP will therefore cause data bus contention.
How should I solve the above two issues?