AM335x gmii_sel.rgmii1_idmode 2ns delay

Alexandru Gagniuc

We're running RGMII1 to an RGMII port on the MT7620.

Clearing the gmii_sel.rgmii1_idmode bit is marked as Reserved, so I am assuming that things will go terribly wrong if I clear it. However, when the bit is cleared, the AM335x outputs a perfectly skewed clock.. With the matching settings on the MT7620, the RGMII link works perfectly.

So my question is, is this supposed to work? Is the internal delay feature an HDL copy-paste that somebody forgot to remove, or is it part of the SoC design? This is a very useful feature, since the internal delay mode on the MT7620 is nowhere near as clean and as reliable.

And of course, this question would not be complete without the obligatory scope captures:

gmii_sel.rgmii1_idmode = 0:

gmii_sel.rgmii1_idmode = 1:

Additional info:

SoC P/N is AM3352BZCZD80. We're using processor-sdk-linux-03.01.00 with hacks to clear the rgmii1_idmode bit.

over 8 years ago

0 Alexandru Gagniuc over 8 years ago

Prodigy 170 points

And the obligatory DTS settings:

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_rgmii1_default>;
	pinctrl-1 = <&cpsw_rgmii1_sleep>;
	status = "okay";
};

&cpsw_emac0 {
	phy-mode = "rgmii-id";
	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

0 peaves over 8 years ago

TI__Guru 62855 points

The MAC provides support for delaying the clock, but this mode was not timing closed at the SOC level during its design. Since timing closure was not performed for this mode of operation, it may not work as expected across all process, voltage, and temperature variations of the device. Therefore, this mode was never provided as a supported feature on AM335x devices.

Regards,
Paul

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AM335x gmii_sel.rgmii1_idmode 2ns delay