AM335X: DDR3 impedance query

Pramey Mhatre

Other Parts Discussed in Thread: AM3352

We are using AM3352 proccessor in our project and we need some details from you which is mentioned below.

1.As per the placement related to Proceesor & DDR3, we are using mirror placement in DDR3 and we have kept the DDR at 14mm away from processor.

2.We are using a 6 Layer Stackup in PCB, where for maintaining a 50 Ohm impedance the trace width we are getting is 6.5mils as given below.

3.As there is a substrate Constraint of minimum 4mils from our side, so is it possible that we keep the trace width of 4 mils with 61.8 Ohm impedance and route the traces in pcb.

Stackup:	6 Layer

Layer	Usage	Thickness	Er Constant	Trace Width	Zo Impedance	Zo Differntial	Trace Width	Gap
	mask	0.5	3.3
	plating	0.5
L1 Comp / Trace	signal	0.5	4.3	6.5	49.8	100	4	4.7
	substrate	4
L2 GND	plane	1	4.3	6	49.1
	substrate	5
L3 VCC	plane	1	4.3	5	50.1
	substrate	39.5
L4 Vref / DDR trace	plane	1	4.3	5	50.1
	substrate	5
L5 GND	plane	1	4.3	6	49.1
	substrate	4
L6 Comp / Trace	signal	0.5	4.3	6.5	49.8	100	4	4.7
	plating	0.5
	mask	0.5	3.3

Our concern is of trace width, as we are not able to route it properly.

over 9 years ago

0 Mariya Petkova over 9 years ago

TI__Expert 4885 points

Hi, Pramey,

Your thread has been moved to Sitara Forum.

Regards,
Mariya

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Yes, as per Table 7-60 from the AM335x Datasheet Rev. J Z0 can be from 50 to 75Ohms.

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hello Biser,

Thanks for your Valuable Answer.

Still I am confused that Datasheet shows the Impedance Typ. value in 50 Ohms and Max value is 75 Ohms.

In this case which impedance value need to follow? Typical Value or the Average of the Typical & Max value.

Please provide suggestion.

Regards,
Pramey

0 Biser Gatchev-XID over 9 years ago in reply to Pramey Mhatre

TI__Guru**** 393215 points

50Ohm is the typically used single-ended impedance. However if it's not suitable for your design you can use a higher impedance <75Ohm. If you have Vtt termination resistors, you must ensure that their value matches the board impedance.

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hello Bisher,

Thanks for your Valuable Answer.

There is one more doubt about it, that if I keep 61.8Ohm impedance for single-ended traces, is it OK that i follow 100Ohm impedance for differential traces.

Regards,
Pramey

0 Biser Gatchev-XID over 9 years ago in reply to Pramey Mhatre

TI__Guru**** 393215 points

They should be = Zo x 2 or 120Ohm in your case.

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hello Bisher,

thanks for your Valuable answer & sorry sorry for delayed reply.

My other Doubt is that for DDR3 I route Address & Data lines with 50Ohm impedance & Clk with 100ohm impedance, as single DDR is used so no termination resistors are there.
So my question is for Clk should i also maintain single ended i.e. 50Ohm impedance for single trace?

i.e. trace width for add, data lines is 6mils=50ohm so should i route clk with 6mils single ended or i follow differential rule of 100ohm?

Is it Possible to match differential impedance of 100ohm without matching single ended impedance of 50ohm?

Regards,
Pramey

0 Biser Gatchev-XID over 9 years ago in reply to Pramey Mhatre

TI__Guru**** 393215 points

DDR_CLK is a differential signal (DDR_CLKP and DDR_CLKN) and should be routed as such, with 100 Ohm diff. impedance. Same applies for DDR_DQSx signals.

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

I am routing address with 6-6-6 rule 50ohm and clk with 4-10-4 rule 100ohm, so by routing clk with 4-10-4 rule i am getting diff. imp. of 100ohm but if i consider clk+/clk- individually with 4-10-4 rule routing i am getting 53.4ohm imp.

So the difference of 53.4ohm & 50ohm is acceptable for clk?

Regards,
Pramey

0 Biser Gatchev-XID over 9 years ago in reply to Pramey Mhatre

TI__Guru**** 393215 points

Single-ended impedance is not that important on differential lines. Besides this, PCB impedance control is typically +/- 5 Ohm, so you are good with 53.4 Ohm too.

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hello Bisher,

My mistake, for previous query i am getting imp of 61.8 ohm in clk for single ended

this is my stackup for PCB, i am following 6mil trace width for 51.7ohm impedance which is around 50ohm i.e. acceptable, for differential i am following 4-4.7-4mils with 100ohm impedance in same layer.

So the difference for this is good to go or not?

0 Biser Gatchev-XID over 9 years ago in reply to Pramey Mhatre

TI__Guru**** 393215 points

Like I said, single-ended impedance doesn't matter for differential lines.

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hi Biser,

I have one more confusion regarding differential impedance & Trace width.
1. for 4 mils of trace width & 4.7 mils of clearance(gap between two traces) i am getting 100 ohms of impedance. That means single ended impedance is 100/2 = 50 ohms.
But if i am routing single ended trace width with the same trace width i.e. 4 mils , i am getting 62 ohms of impedance (why not 50 ohms).
why this difference for the same trace width?

Regards,
Pramey

0 Biser Gatchev-XID over 9 years ago in reply to Pramey Mhatre

TI__Guru**** 393215 points

I already posted twice that single-ended impedance doesn't matter for differential lines. The clock signal is differential, transmitted over both lines. Neither of the clock lines transmits single-ended signal. As for calculating impedances, there are a lot of free tools on the Internet. Personally I like the Saturn PCB toolkit: www.saturnpcb.com/pcb_toolkit.htm

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hi. Biser

This Query for single DDR3 routing

Can i use power plane as reference plane for DDR3 Add/data clk signal?

Or its allowed to change reference plane from ground to power for any signal ?

For single DDR , Does length match consist of A1+A2 +AS= total length or A1+A2=total length

As per Datasheet , Figure 7-55. ADDR_CTRL Routing for Two Single-Side DDR3 Devices

0 Biser Gatchev-XID over 9 years ago in reply to Pramey Mhatre

TI__Guru**** 393215 points

Yes, this is possible, but you must ensure that the reference plane is uninterrupted under the DDR traces. As for single DDR trace length, it's A1+A2

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hi, Biser
thanks for your valuable answer.
But i want to known if i use power plane as reference plane does affect in Signal integrity EMI EMC testing .

Best Regards
Pramey

0 Biser Gatchev-XID over 9 years ago in reply to Pramey Mhatre

TI__Guru**** 393215 points

No, it's an allowed practice.

0 Pramey Mhatre over 9 years ago in reply to Biser Gatchev-XID

Prodigy 150 points

Hi Bisher,

I have a query for Vreference signal, regarding its trace & clearance:
1. what should be the trace width for Vref.
2. what should be the isolation required with other traces, should i maintain it.
3. should i maintain a common trace width if some isolation issues are there.
4. shall i keep gnd/vcc/address/data traces or clock near to it.

Regards,
Pramey Mhatre

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AM335X: DDR3 impedance query