DM8168 SPI interface

Hi Steven,

Do you use DM816x TI EVM or custom board? Do you use EZSDK 5.05.02.00?

See also the below wiki pages which discuss spidev usage:

http://processors.wiki.ti.com/index.php/Linux_Core_SPI_User's_Guide

Regards,
Pavel

Hi Pavel,

I use custom board and DVRRDK v4.0

Does pull-up required for DM8168 SPI interface ? In kernel:

omap_mux_init_signal("spi_d0", OMAP_MUX_MODE0 | OMAP_PULL_UP);
omap_mux_init_signal("spi_d1", OMAP_MUX_MODE0 | OMAP_PULL_UP);

I could try TI DM8168 EVM for test...

But I dont think is custom board issue because another SPI device(LCD module) work perfectly

Thanks

BR,

Steven

Steven Weng1 said:

Does pull-up required for DM8168 SPI interface ? In kernel:

Do you ask for internal or external pull-up? On DM816x TI EVM, SPI_SCS[0] has externall pull-up resistor.

Regards,
Pavel

Hi Pavel,

Thank you!

I have double check the pin mux by reading /debugfs/omap_mux/ setting

omap_mux_init_signal("spi_scs1", OMAP_MUX_MODE0);
omap_mux_init_signal("spi_sclk", OMAP_MUX_MODE0);
omap_mux_init_signal("spi_d0", OMAP_MUX_MODE0);
omap_mux_init_signal("spi_d1", OMAP_MUX_MODE0);

And try "pull-up", "pull-low", "disable pull up/low" setting to pin mux but still dont work.

I still read all zero data  when I connect MISO(master in slave out) pin to SPI device during reading.

I could see data output signal from SPI device by oscilloscope when I disconnect MISO pin during reading.

So I think DM8168 SPI data pin pull the output signal of SPI slave device(maybe the drive strength of this device is too weak?)

I have no idea... so I use four GPIO pins to simulate the SPI signal: CS, CLK, MISO, MOSI. Everything is working...

Does the MISO pin of DM8168 SPI interface have drive strength limitation?

If yes, it seems the SPI device cant drive the signal out,  so we MUST change the SPI interface to gpio pins in our custom board.

Please help me check.

thank you very much.

BR,

Steven

Steven,

Can you provide me the values of PINCTRL166 (clock), PINCTRL168 (cs1), PINCTRL171 (d0) and PINCTRL172 (d1) registers with devmem2 tool?

Steven Weng1 said:

I still read all zero data  when I connect MISO(master in slave out) pin to SPI device during reading.

Is this d0 or d1 pin? Is DM816x McSPI master or slave?

Regards,
Pavel

Steven Weng1 said:

PINCTRL168 (cs1):
Read at address 0x48140A9C (0x4023ca9c): 0x00000000

Do you have external pull-up on the cs1 pin (as TI EVM suggest)? You should remove the internal pull down.

Steven Weng1 said:

I use McSPI driver. it only support master mode?

Yes, DM816x McSPI is master only.

Steven Weng1 said:

I did some modifications to select d0 as MOSI and d1 as MISO in omap2_mcspi_setup_transfer() at drivers/spi/omap2_mcspi.c file, as below:
l |= OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1;
l &= ~(OMAP2_MCSPI_CHCONF_DPE0);

processors.wiki.ti.com/.../TI81XX_PSP_McSPI_Driver_User_Guide

• drivers/spi/omap2_mcspi.c implements core SPI master functionality.
  • This file is generic hence should not modify it.

Steven Weng1 said:

I dont have external pull-up on the cs1 pin but I see the cs1 signal on the oscilloscope work as expected.
So I dont think the external pull-up is root cause. I will try it.

Try with internal pull-up at least, your current configuration is with internal pull down.

Hi Pavel,

From what I understand, you have data on D0/MOSI/TX line, but you do not have any data on D1/MISO/RX line?

Yes.

What is McSPI_CH(1)CONF address? I use devmem2 dump 0x48031140, it's always zero

# devmem2 0x48031140 32

/dev/mem opened.
Memory mapped at address 0x4021d000.
Read at address  0x48031140 (0x4021d140): 0x00000000

I have tried MCSPI_PINDIR_D0_IN_D1_OUT, MCSPI_PINDIR_D1_IN_D0_OUT

The result is the same. use MCSPI_PINDIR_D1_IN_D0_OUT could output correct data output on d0 pin but no data received on d1

Steven,

Steven Weng1 said:

What is McSPI_CH(1)CONF address? I use devmem2 dump 0x48031140, it's always zero

# devmem2 0x48031140 32

/dev/mem opened.
Memory mapped at address 0x4021d000.
Read at address  0x48031140 (0x4021d140): 0x00000000

How did you define that the address is 0x48031140? From what I was able to find, the address is 0x48030140.

Regards,
Pavel

Hi Pavel,

Sorry for late...

Using devmem2 to dump 0x48030140, result as below:

# ./devmem2 0x48030140 w

/dev/mem opened.Unhandled fault: external abort on non-linefetch (0x1018) at 0x402f6140

Memory mapped at address 0x402f6000.

Bus error

Are there something wrong?

BTW, When I use spi_d1 as MISO. If the pinmux mode  is correct and I have tried pull-up/pull-down/disable pull-up(down) in pinmux

Are there any other settings in spi_d1 pin? NEED set input/output mode?(like gpio input/output)

Thanks a lot.

Steven Weng1 said:

Using devmem2 to dump 0x48030140, result as below:

# ./devmem2 0x48030140 w

/dev/mem opened.Unhandled fault: external abort on non-linefetch (0x1018) at 0x402f6140

Memory mapped at address 0x402f6000.

Bus error

Are there something wrong?

Looks like the SPI0 clock (from device PRCM) is not enabled. The strange thing here is how your SPI0 works fine in the other MOSI/MISO mode when it is not enabled!

Check the value in CM_ALWON_SPI_CLKCTRL/0x48181590 register and enable SPI0, see the below set of commands:


root@dm814x-evm:~# devmem2 0x48030140
/dev/mem opened.Unhandled fault: Precise External Abort on non-linefetch (0x1018) at 0x40086140

Memory mapped at address 0x40086000.
Bus error
root@dm814x-evm:~# devmem2 0x48181590
/dev/mem opened.
Memory mapped at address 0x4011d000.
Read at address  0x48181590 (0x4011d590): 0x00030000
root@dm814x-evm:~# devmem2 0x48181590 w 0x2
/dev/mem opened.
Memory mapped at address 0x40275000.
Read at address  0x48181590 (0x40275590): 0x00030000
Write at address 0x48181590 (0x40275590): 0x00000002, readback 0x00000002
root@dm814x-evm:~# devmem2 0x48181590
/dev/mem opened.
Memory mapped at address 0x40270000.
Read at address  0x48181590 (0x40270590): 0x00000002
root@dm814x-evm:~# devmem2 0x48030140
/dev/mem opened.
Memory mapped at address 0x4026f000.
Read at address  0x48030140 (0x4026f140): 0x00060000

Steven Weng1 said:

Are there any other settings in spi_d1 pin?

Only the right value in McSPI_CH1CONF register is needed to set the d1 pin direction.

Regards,
Pavel

Hi Pavel,

Thanks for your reply!

Please help me check:

(1) TI816x support 4 spi channels. There are 4 CS(chip select) pin for choosing SPI bus. All the bus using the same SPI clock. Does I need to configure different clock for 4 channels?

(2) In the arch/arm/mach-omap2/clock816x_data.c, only omap2_mcspi.1 clock configured as below:

    CLK("omap2_mcspi.1",    "ick",            &mcspi1_ick,        CK_TI816X),

    CLK("omap2_mcspi.1",    "fck",        &mcspi1_fck,    CK_TI816X),

    Does the omap2_mcspi.2 need to configure for using CS1(CS0~CS3) spi bus? (I see the clock814x_data.c configure omap2_mcspi.1~omap2_mcspi.4)

(3) How to enable spi clock in CM_ALWON_SPI_CLKCTRL register in the kernel source? Could I check the spi clock is enable by oscilloscope?

(4) After manual enable the spi clock in CM_ALWON_SPI_CLKCTRL register. I could read the MCSPI_CH1CONF(0x48030140) as below:

# devmem2 0x48030140
/dev/mem opened.
Memory mapped at address 0x40167000.
Read at address  0x48030140 (0x40167140): 0x000603C0

0x000603C0 is correct for spi_d0 as MOSI and spi_d1 as MISO.

It is strange that after I reading the SPI bus once, CM_ALWON_SPI_CLKCTRL register return to 0x00030000(spi clock disable)

Hi Pavel,
After go through SPI driver "mcspi", it will disable spi clock after each transfer...
spi clock is disable after register mcspi driver and enable before each transfer.
So I think the spi clock is correct during data transfer and I could output the spi clock as I wish.

Please help me check 0x000603C0 in MCSPI_CH1CONF(0x48030140) is correct in my usage
spi_cs1 for chip select, spi_d0 as MOSI, spi_d1 as MISO
thank you very much

Steven Weng1 said:

(1) TI816x support 4 spi channels. There are 4 CS(chip select) pin for choosing SPI bus. All the bus using the same SPI clock. Does I need to configure different clock for 4 channels?

Steven Weng1 said:

2) In the arch/arm/mach-omap2/clock816x_data.c, only omap2_mcspi.1 clock configured as below:

    CLK("omap2_mcspi.1",    "ick",            &mcspi1_ick,        CK_TI816X),

    CLK("omap2_mcspi.1",    "fck",        &mcspi1_fck,    CK_TI816X),

    Does the omap2_mcspi.2 need to configure for using CS1(CS0~CS3) spi bus? (I see the clock814x_data.c configure omap2_mcspi.1~omap2_mcspi.4)

Steven Weng1 said:

(3) How to enable spi clock in CM_ALWON_SPI_CLKCTRL register in the kernel source? Could I check the spi clock is enable by oscilloscope?

processors.wiki.ti.com/.../TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

You can monitor the SPI_SCLK pin with the oscilloscope.

Steven Weng1 said:

0x000603C0 is correct for spi_d0 as MOSI and spi_d1 as MISO.

Steven Weng1 said:

After go through SPI driver "mcspi", it will disable spi clock after each transfer...
spi clock is disable after register mcspi driver and enable before each transfer.
So I think the spi clock is correct during data transfer and I could output the spi clock as I wish.

Please help me check 0x000603C0 in MCSPI_CH1CONF(0x48030140) is correct in my usage
spi_cs1 for chip select, spi_d0 as MOSI, spi_d1 as MISO

MCSPI_CH1CONF looks to be correct.

So if you are sure that the clock is active during the transfer, next thing you can check is if there is data out from the slave SPI chip. How exactly you define that there is data output from the salve SPI chip on the MISO line?

Regards,
Pavel

Hi Pavel,

The spi clock is correct during the transfer by monitoring the spi_clk pin with the oscilloscope.

How exactly you define that there is data output from the salve SPI chip on the MISO line?

(1) After disconnecting the spi_d1 with MISO line. I could see the data output from the slave SPI chip side on the MISO line with the oscilloscope.

(2) I have tried "jump wire" the 4 GPIO to simulate spi_clk, spi_cs, spi_d0, spi_d1 and use the SPI GPIO driver(in the drivers/spi/spi_bitbang.c) to read the slave SPI chip. It works fine!

So I think that there is data output from the slave SPI chip.

BTW, I have asked FAE from the slave SPI chip , he said that the data input pin of master device MUST be high-z during read process. How about the spi_d1 pin in dm8168 ?

Thanks

BR,

Steven