McSPI is working with EDMA and the performance is good. I’m using SPI1, single channel (CH0) and master mode with TRM mode = “Transmit and Receive”. Being a typical engineer, I wanted to optimize things further. In my application, I only need to do a “Transmit Only” followed by a “Receive Only”. “Transmit Only” works fine but “Receive Only” never starts. BUT if I manually write to the TX0 register after enabling the SPI channel, the “Receive Only” completes. This makes no sense.
My application sets the MCSPI_MODULCTRL register to all 0 except SINGLE=1. Below is the “Transmit Only” sequence:
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Disable SPI channel (set EN=0 in MCSPI_CH0CTRL)
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Set MCSPI_CH0 CONF register FORCE=1 (asserts chip select)
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Initialize EDMA TX ParamSet. Enable EDMA TX SPI channel for event trigger.
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Set MCSPI_XFERLEVEL register to WCNT=length, AFL=0, AEL=0
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Set MCSPI_CH0 CONF register with CLKG=0, FFER=1, FFEW=1,TCS=0, SBPOL=0, SBE=0, SPIENSLV=0, TURBO=1,IS=0,DPE1=0,DPE0=1, DMAR=0, DMAW=1,TRM=2 (Transmit only),WL=7,EPOL=1,CLKD=1,POL=0,PHA=0
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Enable SPI channel (set EN=1 in MCSPI_CH0CTRL)
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Wait for transmit to complete.
Transmit completes correctly. I see the bytes sent on the scope, WCNT got set to 0 in the MCSPI_XFERLEVEL register and the EDMA ISR indicates completion. The “Receive Only” sequence immediately follows:
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Disable SPI channel (set EN=0 in MCSPI_CH0CTRL). MCSPI_CH0 CONF “FORCE” remains set from above.
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Initialize EDMA RX ParamSet. Enable EDMA RX SPI channel for event trigger.
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Set MCSPI_XFERLEVEL register to WCNT=length, AFL=0, AEL=0
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Set MCSPI_CH0 CONF register with CLKG=0, FFER=1, FFEW=1,TCS=0, SBPOL=0, SBE=0, SPIENSLV=0, TURBO=1,IS=0,DPE1=0,DPE0=1, DMAR=1, DMAW=0,TRM=1 (receive only),WL=7,EPOL=1,CLKD=1,POL=0,PHA=0
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Enable SPI channel (set EN=1 in MCSPI_CH0CTRL)
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Wait for receive to complete – it never does. No activity on scope and WCNT doesn’t change.
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Write to MCSPI_TX0. I see activity on the scope then WCNT=0 and the RX EDMA ISR indicate completion.