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GPMC posted write mode vs. NAND controller posted writes

Aaron Spaete
Expert 4401 points

I need some clarifications on GPMC posted write mode.

 
GPMC_CONFIG bit 0 is NANDFORCEPOSTEDWRITE
GPMC_PREFETCH_CONFIG1 bit 0 is AccessMode: "Prefetch Read" 0x0, or "Write-posting Mode" 0x1
 
In the NAND driver, we set the AccessMode to 1 (Write-posting) every time we do a write, and to 0 for reads. Should we set NANDFORCEPOSTEDMODE or not?
 
We have NAND on CS0 (no other devices on GPMC).
 
Maybe an explanation on what "posted mode" means would be useful.
 
If NAND controller and GPMC are on the GPMC bus, how do they effect each other?
Thanks! 
  • 0
    TI__Intellectual 1585 points

    Aaron,

    You should set the NANDFORCEPOSTEDMODE bit.  "Posted mode" simply means that internal buffers are used to store the write transactions, or in the case of read, the "prefetch" data that is read back from the NAND.  This mode exists to optimize performance because it speeds up single accesses to the NAND_COMMAND and NAND_ADDRESS registers.  When the bit is set, GPMC will always send back a response as soon as the OCP write command has been registered, so the CPU does not have to wait for the actual write transfer to external NAND flash to complete.

    Your usage of AccessMode looks to be correct.

    I would direct you to the OMAP35xx technical reference manual (TRM) to find more information: http://focus.ti.com/lit/ug/spruf98g/spruf98g.pdf.

    Specifically, 11.1.5.14.1.2 NAND Device Command and Address Phase Control discusses posted writes.  Section 11.1.5.14.4 Prefetch and Write-Posting Engine (and subsequent sections) have a deeper discussion of the issues.