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C6748 power decoupling recommandations?

Traian Mitrache
Prodigy 180 points

Is there an app note with recommandations on how many and what values decouplig capacitors should be used?

  • 0
    TI__Mastermind 18130 points

    Hi Traian,

    This info is usually in the datasheet, but it seems to be missing from the C6748 doc. I have asked our product group to look into this for you.

  • 0 in reply to TimHarron
    TI__Mastermind 18130 points

    Here are some suggestions I can provide:

    - Ideally you need to try and stay as close as possible to a 1:1 ratio of high freq cap per power pin rule of thumb as possible. If you are careful and follow some basic rules (use the shortest traces possible to the cap, use low ESR (internal resistance) 402 caps, etc.) then it is acceptable to go to a 2 or even a 3 to 1 ratio if you must. 

    - The most important thing is to fit as many caps under the device as possible.  Even if the power pins have to share vias, it's more preferable to share vias and have more caps under the device than to make the cap traces go outside the device footprint to get to the caps.  All the way out there the inductance to the traces make the caps much less effective.

    - As the frequency of the specific power the caps are bypassing goes up, this (capacitor inductance caused by traces) is more and more of an issue.  For our 600 MHz OMAP3 device, for example, it's crucial to get the caps as close as possible.

  • 0 in reply to TimHarron
    Prodigy 180 points

    These are the basic rule of thumb rules, but I was looking for something more specific.

    For example, XILINX has a very detailed table with recommended caps, number of caps, values, etc. for their Spartan 6 devices.

    What do you recommend for the High Frequency decoupling, 0.1uF, 0.01uF, 0.47uF?

    How much bulk cap per supply, pin: is 100uF per VCC rail, on top of the high freq ones enough?

     

     

  • 0 in reply to Traian Mitrache
    TI__Intellectual 1670 points

    Traian,

    I realize this is a late reply, I just got back from summer vacation.

    The number of caps required depends on so many factors that it's impossible to reliably state what the requirement is.  Xilinx may have detailed tables, but in reality they can't say how many caps are required because they don't know your PCB layout, actual caps used, etc.  Their tables are little more than an educated guess.  Perhaps they have stated what they think will be a reliable overkill, but still they can't actually guarantee anything from just the number of certain values of caps.

    What Tim recommended is a good rule of thumb.  As far as the bulk caps, we generally use 10uF bulk caps, and personally I use one of these for about every 10 bypass caps.  The most important thing, as Tim mentions, is to get the least amount of inductance in the PCB traces.  If the traces are short and direct, the number of caps required will be less since each cap will be more effective.

    Another option is to use planer capacitance from an additional PCB layer.  For high speed PCBs this is quickly becoming a common option since this capacitance (that is the result of a power plane close to a ground plane) is the best (least inductive) capacitance available to any device.  If cost is not crucial, this is a great option.  2 mil separation between PCB power and ground layers is often available for no additional cost (except of course the cost of adding two more PCB layers) and does a great job of bypassing.

    I wish I could give you a definite answer, but in reality, the only way of really knowing what performance you'll get is by either simulating the whole power distribution network in a 2D or 3D field solver that's built for the purpose, or actually building it.  All we can state short of that is general guidelines.

    Good luck!

     

  • 0 in reply to Traian Mitrache
    Expert 2270 points

    Traian Mitrache said:

    What do you recommend for the High Frequency decoupling, 0.1uF, 0.01uF, 0.47uF?

    I am beginning to doubt the whole concept of high-frequency decoupling.  0.1uF in 0402 packages are not expensive.  When you compare lower values of 0402s, you can see a little lower high-frequency impedance within a narrow range of high frequencies, but I'm not convinced it's enough to justify using them.  At most frequencies a 0.1uF cap has the same or lower impedance than lower valued caps.  TDK has a tool for comparing components' curves.  I'm going to try using 0.1uF 0402s for high-frequency decoupling. 

    My suspicion is low-value decoupling for high-frequencies only made sense when you couldn't get 0.1uFs in 0402 packages.

     

  • 0 in reply to Charles Gervasi
    TI__Intellectual 1670 points

    Since inductance is the limiting factor for capacitor responsiveness at high frequencies, and inductance varies mostly based on the physical size of a SMT capacitor, many people (including us) are coming to the same conclusion that Charles did, that it doesn't make much sense to use lower values of capacitances when a  higher value is available in the same size. 

    This is why we are recommending 0.1uF in a 402 size for most of our bypass needs.

    It's true that a lower value can give you a tiny peak, or dip really, of lower inductance for a small range of frequencies, but overall the larger value is effective over a larger range of frequencies.

    Keven