power consumption of board OMAP-L138LCDK

Nhan Nguyen55

Other Parts Discussed in Thread: OMAP-L138

Deal all,

My project use a hardware like OMAP-L138LCK kit, and I have problem with power consumption and I focus on the system clock and DDR clock. Right now, system clock is 300Mhz, and DDR clock is 150Mhz.

1. My solutions is switching to by pass mode when the device is not used. The system clock can change while running, and I tested. But seem like DDR clock can not change? Anyone can confirm it for me?

"NOTE: PLLC1 should be configured and a stable clock present on 2X_CLK before releasing the
DDR2/mDDR memory controller from reset" -> this note from TI document.

2. I have an idea about using Share RAM area when device is not used, so i donot have to access to DDR area and this will save many power for device? am I right?

3. When the device start, I recognize that default bootloader take 200mW power, and it seem not right? any idea?

Thanks alot,

Nhan

over 8 years ago

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi,

Can you use the power consumption spread sheet, to verify your use case:
processors.wiki.ti.com/.../OMAP-L138_Power_Consumption_Summary

Best Regards,
Yordan

0 Mukul Bhatnagar over 8 years ago

TI__Guru* 83745 points

Nhan
Yordan pointed you to the power estimation spreadsheet, which is a great tool to do all the what if analysis on power.

On your specific questions

1) You should be able to put PLL1 in bypass mode - please make sure you are following the EMIF/DDR/PLL TRM sections on low power modes. Do also make sure that if you are putting PLL1 in bypass mode or trying to run DDR in self refresh etc you have no reliance on DDR memory for program execution etc. For DDR operational, you need to adhere to min frequency specified in the datasheet - so PLL1 in bypass is only feasible for standby/sleep/no activity type modes.
You may find some code snippets in the following wiki helpful too

processors.wiki.ti.com/.../Power_Module_for_C6748_and_OMAP-L138

2) Yes, you could architect your code to run from internal memory in low power mode, such that the DDR controller and memory can be put in the lowest power mode.

3) ~200 mW may not be completely unreasonable - especially if you are booting up with device running at 300 MHz (via AISCFG etc) instead of running bypass clocks - you can also deduce this from the power estimation depending on your boot , pll, frequency settings etc. For e.g if i assume 1.2V/300 MHz ARM doing low activity, DSP Enabled with 0 % utilization , DDR enabled but no utilization and all other peripherals except for potentially your boot peripheral - you can see total soc power in the vicinity of 200 mW. If your boot setup is not setting up the PLLs or DDR etc - the power could be slightly lower.

Hope this helps.

Regards
Mukul

0 Nhan Nguyen55 over 8 years ago in reply to Mukul Bhatnagar

Intellectual 300 points

Hi Mukul,

Thanks for your help. I understood what you say.

One more question, My board is designed follow OMAP-L138LCDK. I dont put any code to board, but when power on, OMAP-L138 + FLASH + DDR take 120mW. Are there something wrong? My board's schematic is same with OMAP-L138LCDK.

Nhan

0 Mukul Bhatnagar over 8 years ago in reply to Nhan Nguyen55

TI__Guru* 83745 points

Assuming the device came up in bypass clock frequency and all peripherals in the power on reset default state and CVDD at 1.3V - I would expect the power of the processor to be in the range of ~85-90 mW at room temp, so ~30-35 mW for the remaining Flash, DDR etc may be ok?

Are you seeing any functional issues.

If you are not sure about the state of clocks, PLL and various on chip modules and can connect to JTAG, you can also see the state of the PLLs, PSC via the debug gel file

processors.wiki.ti.com/.../OMAP-L1x_Debug_Gel_Files

Hope this helps
Regards
Mukul

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power consumption of board OMAP-L138LCDK