Other Parts Discussed in Thread: OMAPL138
Processor: OMAPL138, DSP C674x
McBSP and EDMA configuration:
1) Slave mode
2) non-continuous mode (TDMA)
3) FS length is 48 clocks , 4*12bits
From the second data slot, the data is shifted by 12 bits,
we can see that the first 12 bits are exactly the last 12bits of the previous slot that are not being sent, due to the shift.
We have tried to disable the McBSP (clear XRST bit on SPCR) by the end of every slot and activate it at the beginning of the slot, but it did not resolve the problem.
We have also tried to clear the event bits on EDMA Registers: ER, EMR, IR, SER, EER, IER (EER and IER were set at the next transmission).
EDMA configured to invoke an interrupt by the end of it's session that calls a callback function, we can see that it happen.