CCS/AM5728: Debugging DDR

Mishra80,

I moved this thread to the Sitara forum as it is closely related to the HW memory interface of the device and the experts here can have better insights.

Regards,
Rafael

Thanks Biser for the reply.

I have started another thread for simile quires now i will be stick to this thread to avoid the complexity.
e2e.ti.com/.../560319


I have successfully set-up the CCS and test the DDR on EVM am572x .

Now I am trying to regenerate the EVM's DDR configuration just to clear my understand on XLS parameters. by following the sprac36.pdf you mentioned in previous post.

I have sharing the link of DDR open source data sheet from where I have derived the values. and the updated XLS for DDR.
www.datasheetspdf.com/.../D2516EC4BXGGB.html
drive.google.com/.../view


I have found some generated values are not matching with SDK files, could you please review, or if you have XLS for EVM please share.

Below is the stucture from the file board/ti/am57xx/board.c and arch/arm/cpu/armv7/omap5/sdram.c respectively.

static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x8000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xcccf36ab,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x409f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};



const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};


Lisa value are generate properly but there are some mismatch in emif_regs values.

Regards,
Shweta

Please post the Excel file here, I cannot access Google drive.

I didn’t find any way to upload XLS here. How do I post the Excel ?

Shweta

Simply drag-and-drop the file in your reply window. I can't work on the images you posted.

SPRAC36_EMIF_EVM.zip

You seem to have some timing values wrong. Also, the PCB trace lengths - are they for your board or for the EVM? Can you post which register values are different from the original GEL file?

Hello Biser,

"const struct dmm_lisa_map_regs" values are same and below are the Uboot structure which is different from original source code:

static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_config2 = 0x8000000,
.sdram_tim1 = 0xcccf36ab,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x409f88a8,

.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
};

For your information I have also load my GEL file and perform read wirte to memory address x80000000, via CCS it is working fine with my GEL as well.

Now I am not able to figure out with what these resister value means and how will it affect the system.
Is minor register change will work in case for DDR ?
What are the bare minimum setting is require to make DDR work ?

Regards,
Shweta

Hello Biser,

Any comment ? what are the possible parameter responsible for this change ? 

Regards,

Shweta

I am out of office till Jan. 4, 2017. I can work on this after that. Sorry for the delay.

Hello Biser,

Hope you have wonderful vacation .
Do you have any comment on above queries.

Regards,
Shweta