sysclkout

Pradeep Naru

Hi,

TMS320C6678ACYPA25 is using in our prototype board.our requirement is DSP SYSCLKOUT should be routed to Virtex-6 FPGA & Kintex-7 FPGA.shall we need to convert single ended to differential?shall we have to use buffer?please clarify on this.

Thank you inadvance.

Pradeep N.

over 9 years ago

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Pradeep,

It should be based on the clocking requirement of the FPGA design. Most of the FPGA has the differential clock inputs, in this case you may need to convert the single ended to differential.

Regards,
Senthil

0 Pradeep Naru over 9 years ago in reply to Senthilkumar Srinivasan

Intellectual 300 points

Senthil,
Thank you for the reply.Can you please suggest a 1:2(1 input,2 outputs) LVCMOS to LVDS converter(part number).

0 Senthilkumar Srinivasan over 9 years ago in reply to Pradeep Naru

TI__Mastermind 43660 points

Praddeep,

I would suggest post your query in below forum to get better response.

e2e.ti.com/.../

Regards,
Senthil

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sysclkout