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DM365 display not getting proper NTSC video

Other Parts Discussed in Thread: TVP5146

Hi All,

We are developing display device driver for DM365 Processor. We are using Rev D Evalution module supplied by Spectrum digital. The display driver is ported from DM6446. In the driver, we have activated NTSC (CVBS) interlace format and using PLL1 for clock generation. After porting and making register changes specific to Dm365 we are seeing that blue component is displayed in green. In the current driver we have enabled only VID0 and framebuffer gets data in RGB888 (24BPP), screen resolution 736X480 and VENC is configured for REC656 mode. Below is the register dump. Why I am getting green component? What is the register setting I am doing wrong. Thanks in advance. The Framebuffer address is 0x86000000

========VPBE OSD Register Dump @ 0x01C70200 ==========
OSD Mode is     0x200
Video Mode is   0x3
OSDWin0 Mode is 0x0
OSDWin1 Mode is 0x0
RectCur Mode is 0xF913
m_VidWin0Off is 0x1045
m_VidWin1Off is 0x0
m_OsdWin0Off is 0x0
m_OsdWin1Off is 0x0
Video Window 01 Address-High register Register 0x30
Video Window 0 Address-Low register Register 0x0
Video Window 1 Address-Low register Register 0x0
OSD Window 01 Address-High register Register 0x0
OSD Window 0 Address-Low register 0x0
OSD Window 1 Address-Low register Register 0x0
m_BasePX is 0x8A
m_BasePY is 0x12
m_VidWin0XP is  0x0
m_VidWin0YP is 0x0
m_VidWin0XL is 0x2E0
m_VidWin0YL is 0xF0
m_VidWin1XP is 0x0
m_VidWin1YP is 0x0
m_VidWin1XL is  0x0
m_VidWin1YL is 0x0
m_OsdWin0XP is 0x0
m_OsdWin0YP is 0x0
m_OsdWin0XL is 0x0
m_OslWin0YL is 0x0
m_OsdWin1XP is 0x0
m_OsdWin1YP is  0x0
m_OsdWin1XL is 0x0
m_OslWin1YL 0x0
m_CurXP is 0x0
m_CurYP is 0x0
m_CurXL is 0x2
m_CurYL is 0x1
m_W0BMP01 is Map 0/1 Register 0x00000000 
m_W0BMP23 is Map 2/3 Register 0x00000000 
m_W0BMP45 is Map 4/5 Register 0x00000000 
m_W0BMP67 is Map 6/7 Register 0x00000000 
m_W0BMP89 is Map 8/9 Register 0x00000000 
m_W0BMPAB is Map A/B Register 0x00000000 
m_W0BMPCD is Map C/D Register 0x00000000 
m_W0BMPEF is Map E/F Register 0x00000000 
m_W1BMP01 is Map 0/1 Register 0x00000000 
m_W1BMP23 is Map 2/3 Register 0x00000000 
m_W1BMP45 is Map 4/5 Register 0x00000000 
m_W1BMP67 is Map 6/7 Register 0x00000000 
m_W1BMP89 is Map 8/9 Register 0x00000000 
m_W1BMPAB is Map A/B Register 0x00000000 
m_W1BMPCD is Map C/D Register 0x00000000 
m_W1BMPEF is Map E/F Register 0x00000000 
m_MiscCtl is 0x00001000
Test mode Register 0x0
Extended mode Register 0x0
m_ClutRamYcb is 0x00000000
m_ClutRamCr is 0x00000000
m_TransPVal is 0x00000000
m_PpVWin0Adr is 0x00000000

========VPSS VPSSCLK Register Dump @ 0x01C70000 ==========
CLKCTRL 0x1

========VPSS VENC Register Dump @ 0x01C70400 ==========
VMOD  0x1003
VIDCTRL 0x0
Video Data Processing Register 0x0
Sync Control Register 0x4000
Horizontal Sync Pulse Width Register 0x0
Vertical Sync Pulse Width Register 0x0
Horizontal Interval Register 0x0
Horizontal Valid Data Start Position Register 0x0
Horizontal Data Valid Range Register 0x0
Vertical Interval Register 0x0
Vertical Valid Data Start Position Register 0x0
Vertical Data Valid Range Register 0x0
Horizontal Sync Delay Register 0x0
Veritcal Sync Delay Register 0x0
YCbCr Control Register 0x1
RGB Control Register 0x0
RGB Level Clipping Register 0xFF00
Line Id Control Register 0x0
Culling line control Register 0x0
LCD Output Signal Control Register 0x0
LCD_AC Signal Control 0x0
DCLK Control Register 0x0
DCLK Pattern 0 Register 0x0
DCLK Pattern 1 Register 0x0
DCLK Pattern 2 Register 0x0
DCLK Pattern 3 Register 0x0
DCLK Auxiliary Pattern 0 Register 0x0
DCLK Auxiliary Pattern 1 Register 0x0
DCLK Auxiliary Pattern 2 Register 0x0
DCLK Auxiliary Pattern 3 Register 0x0
Horizontal DCLK Mask start Register 0x0
Horizontal Auxiliart DCLK Mask Atart Register 0x0
Horizontal DCLK Mask Range Register 0x0
Vertical DCLK Mask Start Register 0x0
Vertical DCLK Mask Range Register 0x0
Caption Control Register 0x0
Caption Data Odd Field Register 0x0
Caption Data Even Field Register 0x0
Video Attribute Data 0 Register 0x0
Video Attribute Data 1 Register 0x0
Video Attribute Data 2 Register 0x0
Video Status Register 0x0
GCP-FRC Table RAM Address Register 0x0
GCP-FRC Table RAM Data Port Register 0x0
DAC Test Register 0x0
YOUT and COUT Levels Register 0x0
Sub-Carrier Programming Register 0x17A
Composite Mode Register 0x0
CVBS Timing Control 0 Register 0x0
CVBS Timing Control 1 Register 0x0
Digital RGB Matrix 0 Register 0x400
Digital RGB Matrix 1 Register 0x57C
Digital RGB Matrix 2 Register 0x159
Digital RGB Matrix 3 Register 0x2CB
Digital RGB Matrix 4 Register 0x6EE
Vertical Data Valid Start Position for Even Field Register 0x0
OSD Clock Control 0 Register 0x1
OSD Clock Control 1 Register 0x2
Horizontal Valid Culling Control 0 Register 0x0
Horizontal Valid Culling Control 1 Register 0x0
OSD Horizontal Sync Adavnced Register 0x0
Clock control Register 0x1
Enable gama correction Register 0x0

 

Regards,

 Abhijit

  • Hello,

    Based on your description above the code segment, it seems that you are feeding RGB888 data to VID0 and disabling all other windows, and you are outputting component RGB (not component YPbPr), is it correct?

    Please elaborate on your statement: "blue component is displayed in green"

    I would suggest your to modify a Spectrum Digital CCS test case and try again (keep it simple). That is much easier to debug.

    Just wondering, what if you swap the G & B? ^_^

     

  • Hi Paul,

    In the current setup, I have not enabled OSDWIND0, OSDWIND1 and VID1. The data to frame buffer is RGB888 and output is configured for CVBS in NTSC mode. From the block diagram I infered that OSD module converts video data into YUV and gives it as input to VENC module. This module generates CVBS, Y and C component out of which, DAC related to CVBS is enabled. The question of RGB output comes in digital mode if I am right.

    I displayed an image with blue backround on to the screen but it is showing green colour on target. After boot up target shows vertical strips of dots, placed at uniform distance. Hope this point may give some more clue.

    I verified the setting of the CCS code and driver and obeserved that there was not much change except color bar. I didn't got chance to execute CCS test file. I will try this optoin also. If any thing I am going wrong in my understanding please correct.

    Thank you for replay,

     Abhijit

  • Sorry Paul I forgot to mention, I tried to re-arrange component as BGR but the result is same, no change in color.

    Regards,

    Abhijit

  •  

    Hi Paul,

     I used CCS code of VPBE loop back test and commented out VPFE related stuff. Following are the experiments that I carried out,

    On the frame buffer I copied 720X480X2  bytes of YUV422 image data which displayed image without any green component.

    I copied all zeros to frame buffer which gave me green color display. If OSD module can convert RGB data into YUV for VIDWIN, this should give me black color.

    Following is the code snipet
         /* Setup Back-End */
        vpbe_init( LOOPBACK, NTSC, COMPOSITE_OUT );

     

        VENC_VIOCTL = 0x2000;    // Enable VCLK (VIDCTL)
        VENC_DCLKCTL = 0x0800;   // Enable DCLK (DCLKCTL)
        VENC_DCLKPTN0 = 0x0001;  // Set DCLK pattern (DCLKPTN0)
        PINMUX1 &= ~0x00400000;  // Set PINMUX for VCLK

        memset((Uint8 *)pu8FrameBufPtr, 0x00, DDR_VIDMEM_SIZE); /* After this step color of display goes in to green */

        /* Here I am copying YUV422 image data that is giving proper output */

    From above observetion, My question is whether VIDWIN0 supports RGB data? In Linux display driver also I am seeing, YUV422 pixel format for VIDWIN0. But in the data sheet it is mentioned that OSD module will convert RGB to YUV422 for VIDWIN0. Please note that in the current setup we have enabled only VIDWIN0. Please help me in this regard.

    Regards,

       Abhijit

  • Hi Abhijit,

    Thank you for carrying on the debugging process during my absence. As far as I know, this is supported. Could you please send me your CCS testcase? I'd like to try it out and see if I can figure out what has happened to you.

  • Hi Paul,

      Thank you very for your interest in solving the problem. I have copied the code of vpbe_loop back with the modification to display frame buffer content. Please copy this code to D:\Projects\DM3xx\Reference\EVMDM365_BSL_RevC\evmdm365_v1\tests\video_loopback_sd\video_loopback_test.c file. Please note that, there is YUV file opened in this file Test_420.yuv. I could not find attachment icon to attach the file in the post. To disable YUV dumping comment macro YUV_DUMP.

    /*
     *  Copyright 2007 by Spectrum Digital Incorporated.
     *  All rights reserved. Property of Spectrum Digital Incorporated.
     */

    /*
     *  Video Loopback Test
     *
     */

    #include "stdio.h"
    #include <stdlib.h>
    #include "tvp5146.h"

    #define NTSC            1
    #define PAL             0

    #define COLORBARS       1
    #define LOOPBACK        0

    #define SVIDEO_OUT      1
    #define COMPOSITE_OUT   0

    /* AKN: Added video memory base and size */
    #define DDR_VIDMEM_OFFSET   (0x6000000U)
    #define DDR_VIDMEM_SIZE     (0xA8C00U) /*720X480X2BPP*/
    /* VIDWIN0 high address */
    #define OSD_VIDWINADH_H    *( volatile Uint32* )( OSD_BASE + 0x28 )

    #define YUV_DUMP 1 /* Dumps YUV data to frame buffer */

    /* AKN: Added to offest in the SDRAM for video memory */
    Uint32 video_buffer = DDR_BASE + DDR_VIDMEM_OFFSET;

    static Uint8 *pu8FrameBufPtr; /* AKN: Pointer for frame buffer */
    void Setup_PLL0_NTSC()
    {
        unsigned int* pll_ctl       = ( unsigned int* )( 0x01c40d00 );
        unsigned int* pll_secctl    = ( unsigned int* )( 0x01c40d08 );
        unsigned int* pll_cmd       = ( unsigned int* )( 0x01c40d38 );
        unsigned int* pll_div5      = ( unsigned int* )( 0x01c40d64 );

        if (0x20 == ((*pll_ctl) & (0x20)))
        {
            printf("PLL is already powered up \n");
        }

        /* Reconfigure SYSCLK6 divider for VENC = 74.25MHz */
        *pll_ctl &= ~0x0002;              // Power up PLL
        *pll_ctl |=  0x0010;              // Put PLL in disable mode
        *pll_ctl &= ~0x0010;              // Take PLL out of disable mode

        *pll_ctl &= ~0x0020;             // Clear PLLENSRC
        *pll_ctl &= ~0x0001;             // Set PLL in bypass
        EVMDM365_waitusec( 150 );

        *pll_ctl |= 0x0008;              // Assert PLL reset
        *pll_ctl &= ~0x0008;             // Take PLL out of reset

        *pll_ctl &= ~0x0010;             // Enable PLL
        EVMDM365_waitusec( 150 );        // Wait for PLL to stabilize

        _wait (100 );

        *pll_secctl  = 0x00470000;       // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
        *pll_secctl  = 0x00460000;       // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
        *pll_secctl  = 0x00400000;       // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
        *pll_secctl  = 0x00410000;       // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1

        *pll_div5    = 0x8015;           // 594/8 -> 74.25MHz VENC

        *pll_cmd |= 0x0001;              // Set GOSET

        EVMDM365_waitusec( 2000 );

        while(! (((PLL0_CONFIG) & 0x07000000) == 0x07000000));  // Wait for PLL to lock

        EVMDM365_waitusec( 2000 );
        *pll_ctl = 0x0001;               // Enable PLL

    }

    #ifdef VPBE_ENABLE
    static void vpfe_init( Uint32 ntsc_pal_mode )
    {
        Uint32 video_buffer = DDR_BASE + ( DDR_SIZE / 2 );
        Uint32 width;
        Uint32 height;

        if ( ntsc_pal_mode == NTSC )
        {
            width   = 720;
            height  = 480;
        }
        else
        {
            width   = 720;
            height  = 480;
        }

        ISIF_SYNCEN =  0x0000;  // Disable VPFE during setup
        ISIF_MODESET = 0x2F84;  // Interlaced, VD priority as negative
        ISIF_HDW     = 0x0000;
        ISIF_VDW     = 0x0000;
        ISIF_PPLN    = 0x02CF;  // 720
        ISIF_LPFR    = 0x020D;  // 526

        /*
         *  sph = 1, nph = 1440, according to the CCDC spec
         *  for BT.656 mode, this setting captures only the 720x480 of the
         *  active NTSV video window
         */
        ISIF_SPH     = 0x0000;
        ISIF_LNH     = width << 1;                 // * Horizontal lines
        ISIF_HSIZE   = width >> 4;                 // Horizontal line offset
        ISIF_SLV0    = 0x0000;                     // Vertical start line
        ISIF_SLV1    = 0x0000;

        ISIF_LNV     = height >> 1;                // Vertical lines
        ISIF_CULH    = 0xffff;                     // Disable culling
        ISIF_CULV    = 0x00ff;

        /*
         *  Interleave the two fields
         */
        ISIF_SDOFST      = 0x0249;                 // Line offset
        ISIF_CADU        = 0x0400;                 // Frame buffer address high
        ISIF_CADL        = 0x0000;                 // Frame buffer address low
        ISIF_REC656IF    = 0x0001;                 // REC656 enabled

        /*
         *  Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position
         */
        ISIF_CCDCFG      = 0x0812;                 // CCD configuration
        ISIF_FMTCFG      = 0x0000;                 // Disable formatter
        ISIF_FMTSPH      = 0x0000;
        ISIF_FMTLNH      = 0x02D0;
        ISIF_FMTSLV      = 0x0000;
        ISIF_FMTLNV      = 0x0000;
        ISIF_SYNCEN      = 0x0003;                 // Enable CCDC
    }
    #endif /* #ifdef VPBE_ENABLE */

    /* ------------------------------------------------------------------------ *
     *                                                                          *
     *  vpbe_init( colorbars/loopback, ntsc/pal, svideo/composite )             *
     *                                                                          *
     * ------------------------------------------------------------------------ */
    static void vpbe_init( Uint32 colorbar_loopback_mode, Uint32 ntsc_pal_mode, Uint32 output_mode )
    {
        Uint32 basep_x;
        Uint32 basep_y;
        Uint32 width;
        Uint32 height;
        Uint32 test;
        Uint32 u32WidthComp;

        if ( ntsc_pal_mode == NTSC )
        {
            basep_x = 122;
            basep_y = 18;
            width   = 720;
            height  = 480;
        }
        else
        {
            basep_x = 132;
            basep_y = 22;
            width   = 720;
            height  = 480;
        }

        printf("Video memory base 0x%x \n", (Uint32)pu8FrameBufPtr);

        /*
         * Setup clocking / DACs
         */

        VDAC_CONFIG         = /*0x081141CF*/0x101941DC;   // Take DACs out of power down mode
        VPSS_CLKCTL         = 0x00000038;   // Enable DAC and VENC clock, both at 27 MHz
        VPSS_VPBE_CLK_CTRL  = 0x00000011;   // Select enc_clk*1, turn on VPBE clk
        VENC_CLKCTL         = 0x00000001;   // Enable venc & digital LCD clock

        /*
         * Setup OSD
         */
         /* AKN: Commnted clut color is not needed */

        OSD_MODE       = 0x000000fc;   // Blackground color blue using clut in ROM0

        OSD_OSDWIN0MD  = 0;            // Disable both osd windows and cursor window
        OSD_OSDWIN1MD  = 0;
        OSD_RECTCUR    = 0;

        /* AKN: Address are specified in multiple of 32 */
        video_buffer = video_buffer >> 5;

        OSD_VIDWIN0OFST = 0x1000 | (width >> 4);
        /* AKN: High address is non-zero */
        OSD_VIDWINADH_H = (video_buffer >> 16) & (0x7F);/*0x0000*/
        /* AKN: Added 16 bit address */
        OSD_VIDWIN0ADR = video_buffer & 0xFFFF/*0x0000*/; /* Lower 16 bits */

        OSD_VIDWINADH  = 0x0000;
        OSD_OSDWIN0ADL = 0x0000; /* Lower 16 bits */
        OSD_BASEPX     = basep_x;
        OSD_BASEPY     = basep_y;
        OSD_VIDWIN0XP  = 0;
        OSD_VIDWIN0YP  = 0;
        OSD_VIDWIN0XL  = width;
        OSD_VIDWIN0YL  = height >> 1;

        OSD_VIDWINMD   = 0x00000003;   // Disable vwindow 1 and enable vwindow 0
                                            // Frame mode with no up-scaling

        /*
         *  Setup VENC
         */
        if ( ntsc_pal_mode == NTSC )
            VENC_VMOD  = 0x00000003;   // Standard NTSC interlaced output
        else
            VENC_VMOD  = 0x00000043;   // Standard PAL interlaced output

        VENC_VDPRO     = colorbar_loopback_mode << 8;
        VENC_VDPRO    |= 0x200;  // 100% Color bars
        VENC_DACTST    = 0;
        VENC_CMPNT |=0x8000; /* Component video RGB */

        /*
         *  Choose Output mode
         */
        if ( output_mode == COMPOSITE_OUT )
            VENC_DACSEL = 0x00000000;
        else if ( output_mode == SVIDEO_OUT )
            VENC_DACSEL = 0x00004210;


    #ifdef DUMP_REG_VALUES
        printf("OSD_VIDWINADH_H 0x%x, addr 0x%x \n", OSD_VIDWINADH_H, &OSD_VIDWINADH_H);
        printf("OSD_OSDWIN0ADL 0x%x, addr 0x%x \n", OSD_OSDWIN0ADL, &OSD_OSDWIN0ADL);
        printf("OSD_VIDWIN0OFST 0x%x, addr 0x%x \n", OSD_VIDWIN0OFST, &OSD_VIDWIN0OFST);
        printf("VDAC_CONFIG 0x%x, addr 0x%x \n", VDAC_CONFIG, &VDAC_CONFIG);
        printf("VPSS_CLKCTL 0x%x, addr 0x%x \n", VPSS_CLKCTL, &VPSS_CLKCTL);
        printf("VPSS_VPBE_CLK_CTRL 0x%x, addr 0x%x\n", VPSS_VPBE_CLK_CTRL, &VPSS_VPBE_CLK_CTRL);
        printf("VENC_CLKCTL 0x%x, addr 0x%x\n", VENC_CLKCTL, &VENC_CLKCTL);
        printf("OSD_MODE 0x%x, addr 0x%x\n", OSD_MODE, &OSD_MODE);
        printf("OSD_OSDWIN0MD 0x%x, addr 0x%x\n", OSD_OSDWIN0MD, &OSD_OSDWIN0MD);
        printf("OSD_OSDWIN1MD 0x%x, addr 0x%x\n", OSD_OSDWIN1MD, &OSD_OSDWIN1MD);
        printf("OSD_RECTCUR 0x%x, addr 0x%x\n", OSD_RECTCUR, &OSD_RECTCUR);
        printf("OSD_VIDWIN0OFST 0x%x, addr 0x%x\n", OSD_VIDWIN0OFST, &OSD_VIDWIN0OFST);
        printf("OSD_VIDWINADH_H 0x%x, addr 0x%x\n", OSD_VIDWINADH_H, &OSD_VIDWINADH_H);
        printf("OSD_VIDWIN0ADR 0x%x, addr 0x%x\n", OSD_VIDWIN0ADR, &OSD_VIDWIN0ADR);
        printf("OSD_BASEPX 0x%x, addr 0x%x\n", OSD_BASEPX, &OSD_BASEPX);
        printf("OSD_BASEPY 0x%x, addr 0x%x\n", OSD_BASEPY, &OSD_BASEPY);
        printf("OSD_VIDWIN0XP 0x%x, addr 0x%x\n", OSD_VIDWIN0XP, &OSD_VIDWIN0XP);
        printf("OSD_VIDWIN0YP 0x%x, addr 0x%x\n", OSD_VIDWIN0YP, &OSD_VIDWIN0YP);
        printf("OSD_VIDWIN0XL 0x%x, addr 0x%x\n", OSD_VIDWIN0XL, &OSD_VIDWIN0XL);
        printf("OSD_VIDWIN0YL 0x%x, addr 0x%x\n", OSD_VIDWIN0YL, &OSD_VIDWIN0YL);
        printf("OSD_VIDWINMD 0x%x, addr 0x%x\n", OSD_VIDWINMD, &OSD_VIDWINMD);
        printf("VENC_VMOD 0x%x, addr 0x%x\n", VENC_VMOD, &VENC_VMOD);
        printf("VENC_VDPRO 0x%x, addr 0x%x\n", VENC_VDPRO, &VENC_VDPRO);
        printf("VENC_DACTST 0x%x, addr 0x%x\n", VENC_DACTST, &VENC_DACTST);
        printf("VENC_DACSEL 0x%x, addr 0x%x\n", VENC_DACSEL, &VENC_DACSEL);
    #endif /* #ifdef DUMP_REG_VALUES */
    }


    /* ------------------------------------------------------------------------ *
     *                                                                          *
     *  video_loopback_test( )                                                  *
     *                                                                          *
     *                                                                          *
     *                                                                          *
     * ------------------------------------------------------------------------ */
    Int16 video_loopback_test( )
    {

        Uint32 u32Cnt;

    #ifdef YUV_DUMP
        FILE *fpRead;
        Uint8 u8Yuvdata;
    #endif /*YUV_DUMP*/

        /* Reconfigure SYSCLK6 divider for VENC = 27MHz */
        Setup_PLL0_NTSC();

    #ifdef VPBE_ENABLE
        /* Setup Front-End */
        EVMDM365_CPLD_rset(3, 0x05);  // Select TVP5416 on decoder MUX
        tvp5146_init( NTSC, COMPOSITE_OUT );
        vpfe_init( NTSC );
    #endif

        pu8FrameBufPtr = (Uint8 *)video_buffer; /* Pointer for frame buffer */

         /* Setup Back-End */
        vpbe_init( LOOPBACK, NTSC, COMPOSITE_OUT );
        printf("0x%x\n", (Uint32)pu8FrameBufPtr);

        VENC_VIOCTL = 0x2000;    // Enable VCLK (VIDCTL)
        VENC_DCLKCTL = 0x0800;   // Enable DCLK (DCLKCTL)
        VENC_DCLKPTN0 = 0x0001;  // Set DCLK pattern (DCLKPTN0)
        PINMUX1 &= ~0x00400000;  // Set PINMUX for VCLK
        PINMUX1 |= 0XAA00;
        OSD_MISCCTL |= 0x10;
        printf("Clut Ram 0x%x \r\n", OSD_CLUTRAMYCB);

        /* AKN: Write all zeros to frame buffer, after this point display shows green*/
        memset((Uint8 *)pu8FrameBufPtr, 0x00, DDR_VIDMEM_SIZE);

    #if DUMP_REG_VALUES
        printf("VENC_VIOCTL 0x%x, addr 0x%x\n", VENC_VIOCTL, &VENC_VIOCTL);
        printf("VENC_DCLKCTL 0x%x, addr 0x%x\n", VENC_DCLKCTL, &VENC_DCLKCTL);
        printf("VENC_DCLKPTN0 0x%x, addr 0x%x\n", VENC_DCLKPTN0, &VENC_DCLKPTN0);
        printf("PINMUX1 0x%x, addr 0x%x \n", PINMUX1, &PINMUX1);
    #endif

    #ifdef YUV_DUMP
        /* Populate the frame buffer with YUV422 data */
        fpRead = fopen("E:\\Test_420.yuv", "rb"); /* Read YUV file */
        /* fpRead = fopen("E:\\imagescacspnl9_RGB88.RGB", "rb"); */

        if (NULL == fpRead)
        {
            printf("Unable to read YUV file \r\n");
        }
        else
        {
            /* Copy one frame of YUV file one by one */
            for (u32Cnt = 0; u32Cnt < DDR_VIDMEM_SIZE; u32Cnt++)
            {

                if (0 == feof(fpRead))
                    u8Yuvdata = fgetc(fpRead);
                else
                    break;

                *pu8FrameBufPtr = u8Yuvdata;           
                pu8FrameBufPtr++;
                if((DDR_VIDMEM_SIZE - 1) == u32Cnt)
                {
                    printf("Last value \n");
                }
            }

            if (NULL != fpRead)
                fclose(fpRead);

        }
    #endif /*#ifdef YUV_DUMP*/

        return 0;
    }

    Regards,

     Abhijit