Hi All,
We are developing display device driver for DM365 Processor. We are using Rev D Evalution module supplied by Spectrum digital. The display driver is ported from DM6446. In the driver, we have activated NTSC (CVBS) interlace format and using PLL1 for clock generation. After porting and making register changes specific to Dm365 we are seeing that blue component is displayed in green. In the current driver we have enabled only VID0 and framebuffer gets data in RGB888 (24BPP), screen resolution 736X480 and VENC is configured for REC656 mode. Below is the register dump. Why I am getting green component? What is the register setting I am doing wrong. Thanks in advance. The Framebuffer address is 0x86000000
========VPBE OSD Register Dump @ 0x01C70200 ==========
OSD Mode is 0x200
Video Mode is 0x3
OSDWin0 Mode is 0x0
OSDWin1 Mode is 0x0
RectCur Mode is 0xF913
m_VidWin0Off is 0x1045
m_VidWin1Off is 0x0
m_OsdWin0Off is 0x0
m_OsdWin1Off is 0x0
Video Window 01 Address-High register Register 0x30
Video Window 0 Address-Low register Register 0x0
Video Window 1 Address-Low register Register 0x0
OSD Window 01 Address-High register Register 0x0
OSD Window 0 Address-Low register 0x0
OSD Window 1 Address-Low register Register 0x0
m_BasePX is 0x8A
m_BasePY is 0x12
m_VidWin0XP is 0x0
m_VidWin0YP is 0x0
m_VidWin0XL is 0x2E0
m_VidWin0YL is 0xF0
m_VidWin1XP is 0x0
m_VidWin1YP is 0x0
m_VidWin1XL is 0x0
m_VidWin1YL is 0x0
m_OsdWin0XP is 0x0
m_OsdWin0YP is 0x0
m_OsdWin0XL is 0x0
m_OslWin0YL is 0x0
m_OsdWin1XP is 0x0
m_OsdWin1YP is 0x0
m_OsdWin1XL is 0x0
m_OslWin1YL 0x0
m_CurXP is 0x0
m_CurYP is 0x0
m_CurXL is 0x2
m_CurYL is 0x1
m_W0BMP01 is Map 0/1 Register 0x00000000
m_W0BMP23 is Map 2/3 Register 0x00000000
m_W0BMP45 is Map 4/5 Register 0x00000000
m_W0BMP67 is Map 6/7 Register 0x00000000
m_W0BMP89 is Map 8/9 Register 0x00000000
m_W0BMPAB is Map A/B Register 0x00000000
m_W0BMPCD is Map C/D Register 0x00000000
m_W0BMPEF is Map E/F Register 0x00000000
m_W1BMP01 is Map 0/1 Register 0x00000000
m_W1BMP23 is Map 2/3 Register 0x00000000
m_W1BMP45 is Map 4/5 Register 0x00000000
m_W1BMP67 is Map 6/7 Register 0x00000000
m_W1BMP89 is Map 8/9 Register 0x00000000
m_W1BMPAB is Map A/B Register 0x00000000
m_W1BMPCD is Map C/D Register 0x00000000
m_W1BMPEF is Map E/F Register 0x00000000
m_MiscCtl is 0x00001000
Test mode Register 0x0
Extended mode Register 0x0
m_ClutRamYcb is 0x00000000
m_ClutRamCr is 0x00000000
m_TransPVal is 0x00000000
m_PpVWin0Adr is 0x00000000
========VPSS VPSSCLK Register Dump @ 0x01C70000 ==========
CLKCTRL 0x1
========VPSS VENC Register Dump @ 0x01C70400 ==========
VMOD 0x1003
VIDCTRL 0x0
Video Data Processing Register 0x0
Sync Control Register 0x4000
Horizontal Sync Pulse Width Register 0x0
Vertical Sync Pulse Width Register 0x0
Horizontal Interval Register 0x0
Horizontal Valid Data Start Position Register 0x0
Horizontal Data Valid Range Register 0x0
Vertical Interval Register 0x0
Vertical Valid Data Start Position Register 0x0
Vertical Data Valid Range Register 0x0
Horizontal Sync Delay Register 0x0
Veritcal Sync Delay Register 0x0
YCbCr Control Register 0x1
RGB Control Register 0x0
RGB Level Clipping Register 0xFF00
Line Id Control Register 0x0
Culling line control Register 0x0
LCD Output Signal Control Register 0x0
LCD_AC Signal Control 0x0
DCLK Control Register 0x0
DCLK Pattern 0 Register 0x0
DCLK Pattern 1 Register 0x0
DCLK Pattern 2 Register 0x0
DCLK Pattern 3 Register 0x0
DCLK Auxiliary Pattern 0 Register 0x0
DCLK Auxiliary Pattern 1 Register 0x0
DCLK Auxiliary Pattern 2 Register 0x0
DCLK Auxiliary Pattern 3 Register 0x0
Horizontal DCLK Mask start Register 0x0
Horizontal Auxiliart DCLK Mask Atart Register 0x0
Horizontal DCLK Mask Range Register 0x0
Vertical DCLK Mask Start Register 0x0
Vertical DCLK Mask Range Register 0x0
Caption Control Register 0x0
Caption Data Odd Field Register 0x0
Caption Data Even Field Register 0x0
Video Attribute Data 0 Register 0x0
Video Attribute Data 1 Register 0x0
Video Attribute Data 2 Register 0x0
Video Status Register 0x0
GCP-FRC Table RAM Address Register 0x0
GCP-FRC Table RAM Data Port Register 0x0
DAC Test Register 0x0
YOUT and COUT Levels Register 0x0
Sub-Carrier Programming Register 0x17A
Composite Mode Register 0x0
CVBS Timing Control 0 Register 0x0
CVBS Timing Control 1 Register 0x0
Digital RGB Matrix 0 Register 0x400
Digital RGB Matrix 1 Register 0x57C
Digital RGB Matrix 2 Register 0x159
Digital RGB Matrix 3 Register 0x2CB
Digital RGB Matrix 4 Register 0x6EE
Vertical Data Valid Start Position for Even Field Register 0x0
OSD Clock Control 0 Register 0x1
OSD Clock Control 1 Register 0x2
Horizontal Valid Culling Control 0 Register 0x0
Horizontal Valid Culling Control 1 Register 0x0
OSD Horizontal Sync Adavnced Register 0x0
Clock control Register 0x1
Enable gama correction Register 0x0
Regards,
Abhijit