Tool/software: Code Composer Studio
Hello,
We use C6657 with two DDR3(MT41K128M16JT-125IT). C6657 Core CLK input is 100MHz, and DDR_CLK input is 60MHz. We use Memory_test pjt from STK_C6657.7z downloaded from the forum, and modify some places.
In original KeyStone_DDR_Init.c the C6657_EVM_DDR_Init function is as belwo:
gpBootCfgRegs->DDR3_CONFIG_REG[2~5]=***
gpBootCfgRegs->DDR3_CONFIG_REG[14~17]=***
Which corresponds to Lane0~4.
We use DDR3 PHY Calc v10.xlsx (downloaded from this forum) to calculate DDR3 leveling parameters. When we input Lane0~3 routing length, and see Registers’values for Lane4~7 change. We use new parameters from the .xlsx file and the test fails. We think DDR3_CONFIG_x and Byte lane do not match as described in SPRUGV8D.
Is there any other calc file/tool for C6657 DDR3?
Thanks a lot!
