TMS320C6678: Bootmodes without using IBL

Rams

Part Number: TMS320C6678
Other Parts Discussed in Thread: 66AK2H12

Hi,

We have a C6678 TMDSEVM6678L REV 3B EVM.

1) Is that possible to boot C6678 without IBL for custom design? If so, what bootmodes can be tested with C6678 EVM without IBL?

2) The BIOS MCSDK User guide 2.0 describes supported bootmodes for C6678 EVM

processors.wiki.ti.com/.../BIOS_MCSDK_2.0_User_Guide

The above link shows three boot modes which which do not require IBL over I2C bus 0x51. (Ethernet, SRIO and PCIe boot). But it is mentioned that IBL ethernet configurations are required for ethernet boot. Please clarify why ethernet boot requires IBL configuration?

Is that possible to test ethernet and PCIe boot on C6678 EVM without involving IBL?

Please let us know the setup procedures for PCIe, Ethernet and SPI NOR boot modes for C6678 EVM

3) In one of the e2e forum, C6667 hardware setup was referred for DIP switch settings for ethernet and PCIe boot modes.

http://processors.wiki.ti.com/index.php/TMDXEVM6678L_EVM_Hardware_Setup#Boot_Mode_Dip_Switch_Settings

This shows ROM SPI boot, ROM SRIO boot, ROM Ethernet Boot, ROM PCIE boot. The documentation and naming conventions are not consistent and it was confusing to read initially. When we see Ethernet boot mode and EMAC boot mode, it was difficult to understand as both are ethernet based. In some places EMAC boot mode is called IBL TFTP which at least makes sense.

Can we test SPI NOR boot mode using C6678 EVM?

4) For ROM boot modes, how will DDR be initialized and other initialization will be done in this case? ( We already have a custom board based on 66Ak2H12 and ARM does the setup of queues and DDR3B initialization)

We just want to test three use cases:-

1) SPI NOR boot - Is that possible to keep the init code for DSPs and DDR and application images in SPI NOR Flash?

2) PCIe boot - How do we setup PCIe boot, how can we initialize the DSP. Once DSP cores and DDR are initialized, we can load the cores with application images from host CPU.

3) Ethernet Boot - Initialize the DSP cores and DDR. Load the DSP with application images from host CPU

Thanks

Rams

over 9 years ago

0 Yordan Kovachev over 9 years ago

TI__Guru**** 161600 points

Hi Rams,

I've notified the design team. Feedback will be posted here.

Best Regards,
Yordan

0 Rahul Prabhu over 9 years ago

TI__Guru** 116920 points

Rams,

The IBL workaround was primarily introduced to this device to work around ROM bootloader Advisor issues (eg PLL initialization, Serdes init) and to support certain features that were not supported on in the ROM bootloader as the initial design didn`t required these features (for eg TFTP and NAND boot).

SPI NOR and Ethernet boot can be supported on this device without the need for IBL. For examples, you can refer to :

SPI NOR boot example on EVM without IBL:
processors.wiki.ti.com/.../KeystoneI_Bootloader_Resources_and_FAQ

Ethernet boot example without IBL:
processors.wiki.ti.com/.../Processor_SDK_RTOS_BOOT_C66x

Please note the DDR initialization though part of the ROM bootloader process is not recommended on this device as it doesn`t support hardware leveling and also the DDR Initialization sequence for this device was modified after the ROM bootloader was finalized. However, there have been lot of customer who have successfully initialized DDR on these parts at lower speeds loaded the application and then re-initialized the DDR with hardware leveling and increased speeds.

An example of DDR initialization using SPI NOR boot image on C66x is provided in the link below:
processors.wiki.ti.com/.../KeystoneI_Bootloader_Resources_and_FAQ

Note that example is for C6657 and not for C6678. the DDR configuration table for both these devices is different. Please refer to the tiboot_c6678.h file provided in ibl/src for the configuration table for your device.

Hope this helps

Regards,
Rahul

0 Rams over 9 years ago in reply to Rahul Prabhu

Expert 1800 points

Hello Rahul,

Thanks for the detailed information. As per processors.wiki.ti.com/.../KeystoneI_Bootloader_Resources_and_FAQ, if we are using PG 2.0 C6678 silicon we can skip IBL for ROM Boot modes.

1) Do you recommend adding SPI NOR boot mode for custom design to initialize the DSP and load the application code to the cores via PCIe or ethernet mode? Or it is safe to skip SPI NOR boot mode.

2) You have indicated that DDR initialization is not recommended as part of ROM bootloader process. If we use PCIe or Ethernet bootmodes , we should still be able to do DDR initialization as part of PCIe boot or Ethernet boot right?

3) I have see the example codes for PCIe boot and ethernet boot. If we have to provide DDR init parameters for our custom board, how do we do that. In the PCIe example project, how do you include DDR init parameters?
For the ethernet boot, how do you include DDR init code?

Please clarify

Thanks
Rams

0 Rahul Prabhu over 9 years ago in reply to Rams

TI__Guru** 116920 points

Yes, you can add SPI NOR boot mode to your custom design to initialize the DSP. Many users of this device have used this memory to go to production.

My under standing is direct PCIe boot mode has an issue with the serdes configuration due to which the IBL implements a PCIE init workaround code using function iblPCIeWorkaround() in the file pdk_c667x_x_0_x\packages\ti\boot\ibl\src\device\c66x\c66xinit.c.

Yes, you can do DDR init with ethernet and PCIE boot as well. This has been demonstrated using the example Srioboot_ddrinit example in the SDK. This uses the platform library to initialize the DDR and then copies code and runs slave cores.

 /* Initialize main Platform lib */
    memset(&init_config, 0, sizeof(platform_init_config));
    memset(&init_flags, 1, sizeof(platform_init_flags));
    init_flags.phy = 0;
    if (platform_init(&init_flags, &init_config) != Platform_EOK)
    {
        printf ("Platform init failed!\n");
        return;
    }

There are 2 ways of performing DDR initialization. If you are using ROM to do this you need to provide a DDR configuration table and place it at the pre-defined location as specified in the device datasheet. This is demonstrated in the C6657 SPI boot example with DDR on the wiki that I provided.

processors.wiki.ti.com/.../File:C6657_directROM_Boot_example.zip

2nd way to do this is to use platform library to initialize the DDR as described earlier in my response. The second approach is easier to debug as it uses user level code instead of bootROM to initialize the DDR. Also, since this is a custom board, we recommend you create a GEL file to test the DDR initialization before you modify the platform library or the DDR configuration table.

Regards,

Rahul

PS: You may want to prototype your boot setup on the EVM before trying this out directly on the custom board.

0 Rams over 9 years ago in reply to Rahul Prabhu

Expert 1800 points

Hello Rahul,

Thanks for the clarification. We would prototype the boot setup on the EVM before trying it directly on ths custome board.

1) If we use SPI boot mode to initialize the DSP , it will be still possible to load DSP application on different cores using PCIe right?
2) How can we reset individual cores. Is soft reset possible in this case or we should do only PCIe local reset? Is soft reset possible on individual cores?

Regards
Rams

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TMS320C6678: Bootmodes without using IBL