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66AK2E05: TSREFCLOCK use ?

Tarang Jindal68
Intellectual 820 points
Part Number: 66AK2E05


There is diff clock signals (TSREFCLKP/N) in K2E SoC.

According to datasheet, TSREFCLK is a input clock for SyncE.

As, SGMII interface supporting SyncE inside, so why this external clock is required?

If, I am supporting a SGMII interface and the selected PHY has SyncE support, then is it required to provide TSREFCLK or not? Please also provide the reason.

Thanks and Regards

Tarang Jindal

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the SGMII experts. their feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Guru 50170 points

    Hi, Tarang,

    From our Hardware Apps Engineer:

    SyncE has two methods of implementation.

     

    1. What we call “HW DPLL” implementation or,

    2. “SW DPLL”.

     

    #1 requires programming the recovered SyncE clocks to be directed to the device output pins where an external HW DPLL (that complies with ITU8262 ECC Option1 & Option2 clock wander and jitter requirements) will filter and feedback the clocks into SERDES clock input.

     

    #2 requires programming the recovered clocks to be forwarded to the CPTS inside CPSW. CPTS will generate timestamps that SW can read and track for a SW DPLL implementation. SW DPLL will use SPI -> DAC -> VTCXO route to feed back the clock into SERDES. In this case, TSREFCLK is needed to drive CPTS.

     

    TSREFCLK therefore, is not to be confused with the SyncE SERDES recovered clocks.

     

    Does this make sense?