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66AK2E05: Maximum supported valid system clock speed?

Tarang Jindal68
Intellectual 820 points
Part Number: 66AK2E05


Hello,

I am using 66AK2E05ABDA25 SoC.

According to part number, the Maximum device speed can be 1.25GHz.

There is a register given in datasheet - Device Speed (DEVSPEED) Register

According to this register, Device speed can be 800MHz, 1000MHz, 1200MHz, 1350MHz, 1400MHz.

There is no value as 1250MHz.

So, it creates a doubt that what will be the maximum possible device speed - 1.2GHz or 1.25GHz. (for 66AK2E05ABDA25)
Please clear this doubt.

Thanks and Regards

Tarang Jindal

  • 0
    TI__Mastermind 42545 points

    Hi Tarang,

    Thanks for pointing that out. I will investigate the settings in the DEVSPEED register and get back to you as soon as I have some information.

    Regards,

    Bill

  • 0
    TI__Guru**** 161600 points

    Hi Tarang,

    This is strange indeed. However I think that 1.2 GHz is the max speed, since on both TI Product folder () & in the Data Manual (Section 1.1 Features) there are the following statements:

    ARM® Cortex®-A15 MPCore™  CorePac

      -Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz

    One TMS320C66x DSP Core Subsystem (C66x CorePacs), Each With

     - 1.4 GHz C66x Fixed/Floating-Point DSP Core

        - 38.4 GMacs/Core for Fixed Point @ 1.2 GHz

        - 19.2 GFlops/Core for Floating Point @ 1.2 GHz

    However, I will notify the design team to elaborate on this discrepancy. You can also use the Submit Documentation Feedback link at the bottom of the pages, to report this directly. 

    Best Regards, 
    Yordan

  • 0
    TI__Mastermind 42545 points
    Hi Tarang,
    There is some history to this question. Originally the 66AK2E05 was designed to be a 1.2GHz component. The value in the DEVSPEED register is used by the rom boot loader to determine the PLL settings needed to configure the device for the 'maximum speed' at the boot time. Using some of the bootmode bits to determine the frequency of the sysclk provided, the PLL is configured to match the speed of the value in the DEVSPEED register. This allows a device to be booted at an optimum speed at startup.
    Once we had silicon and started characterizing the part, it became clear that it would operate at 1.25GHz so the data manual was changed to reflect that speed. Unfortunately, the PLL settings controlled by the DEVSPEED register are programmed into the rom boot loader and couldn't be changed without updating the silicon. It was decided that the part would boot at 1.2GHz for the 1.25GHz variant. If you want to gain that extra 0.05GHz, you will need to reprogram the PLL after the device has booted to the values needed for 1.25GHz.
    So, to answer the original question, the devices will operate up to 1.25GHz but we don't have a DEVSPEED value that will boot the device at that speed.
    Regards,
    Bill
  • 0 in reply to Bill Taboada
    Intellectual 820 points
    Hello Bill,

    I understood that, the device can operate at 1.25Mhz but the manual device speed reg is not updated.

    I have also found one "K2E_Clocking_Spreadsheet_v1.0_may2015".
    The spreadsheet has given the PLL settings and clock register settings to get any desire clock rates.

    In MAINPLL tab,
    There is a tab to selected the device speed, which only shows - 800MHz/1000MHz/1200MHz.
    so, if we need 1250MHz core clock, what will be the PLL (PLLD, PLLM, CLKOD) settings for that.

    Thanks and Regards
    Tarang Jindal
  • 0 in reply to Tarang Jindal68
    TI__Mastermind 42545 points

    Hi Tarang,

    I'll check and see why the spreadsheet hasn't been updated. If you select the 1200MHz setting you will see that the 100MHz clock is multiplied up to 2400MHz. Simply change the PLLM value to 24 to multiply the 100MHz clock to 2500MHz for a 1250MHz SYSCLK1. This assumes you are using a 100MHz SYSCLK input. For more information, please refer to the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. H).

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    Intellectual 820 points

    Hello Bill, 

    yes we are using 100 Mhz core clock. I tried this option (setting PLLM value to 24) in spreadsheet. This gives 1250 MHz clock with a error "OUT OF RANGE". probably because we have set the device speed 1200 MHz.

    As you mentioned that the spreadsheet is not updated, so i assume that with the registers settings for 1250MHz , the SoC can operate on maximum of 1250 MHz.  

    Thanks  and Regards

    Tarang Jindal