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66AK2E05: K2E SoC System Clock architecture

Tarang Jindal68
Intellectual 820 points
Part Number: 66AK2E05

Hello, 

According to K2E device manual, 

The Core clock is used to generate the system clock. there are 4 system clocks generated by the internal PLL. 

The system clock is used for various peripherals depending upon the internal clock dividers. (on page-230, Table-11-13)

According to that table, SYSCLK1 is used for SGMII, XFI, Hyperlink, USB etc. 

There is also external clock ports for the SGMII, XFI, hyperlink and USB interfaces. 

so, i have a doubt that, if we use the SYSCLK1 for these peripherals then why there is a requirement of dedicated external clocks for these interfaces.

is this SYSCLK1 providing the any other functionality for these interfaces? If yes then what it is? 

Thanks and Regards

Tarang Jindal

  • 0
    TI__Guru 65405 points
    Hi Tarang Jindal,

    I've forwarded this to the design team. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Mastermind 42545 points
    Hi Tarang,
    The SYSCLK1 provides the clocking for the circuit that interfaces between the serdes peripheral and the internal VBUS for data transfer. It is not used to provide the clocking to the serdes interface circuit. That requires the dedicated external clock input. Since that is the clock used to generate the serdes interface signals, it has a more stringent jitter requirement.
    Regards,
    Bill